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authorMayank Rana <mrana@codeaurora.org>2016-03-16 21:38:29 -0700
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-23 21:25:06 -0700
commit07be828dfe261a8c1688d47734f0651646f3de1b (patch)
tree2fa348dc704f7632aac253292f4aa0106ceda2a4 /drivers/usb
parentb174de95589d33c67f1316723d46c71d1e72ba85 (diff)
usb: phy: qmp: Remove both phy_clk_scheme based init functionality
Currently QMP PHY driver expects to have both se_clk and diff_clk based PHY initialization sequence from devicetree. This change removes need of both phy_clk_scheme based init sequence as on newer platform QMP PHY only uses one of phy_clk_scheme. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/phy/phy-msm-ssusb-qmp.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/usb/phy/phy-msm-ssusb-qmp.c b/drivers/usb/phy/phy-msm-ssusb-qmp.c
index f90998c72560..873051fcd527 100644
--- a/drivers/usb/phy/phy-msm-ssusb-qmp.c
+++ b/drivers/usb/phy/phy-msm-ssusb-qmp.c
@@ -83,11 +83,10 @@ unsigned int qmp_phy_rev2[] = {
[USB3_PHY_START] = 0x608,
};
-/* reg values to write based on the phy clk scheme selected */
+/* reg values to write */
struct qmp_reg_val {
u32 offset;
- u32 diff_clk_sel_val;
- u32 se_clk_sel_val;
+ u32 val;
u32 delay;
};
@@ -487,7 +486,6 @@ static int configure_phy_regs(struct usb_phy *uphy,
{
struct msm_ssphy_qmp *phy = container_of(uphy, struct msm_ssphy_qmp,
phy);
- bool diff_clk_sel = true;
if (!reg) {
dev_err(uphy->dev, "NULL PHY configuration\n");
@@ -495,9 +493,7 @@ static int configure_phy_regs(struct usb_phy *uphy,
}
while (reg->offset != -1) {
- writel_relaxed(diff_clk_sel ?
- reg->diff_clk_sel_val : reg->se_clk_sel_val,
- phy->base + reg->offset);
+ writel_relaxed(reg->val, phy->base + reg->offset);
if (reg->delay)
usleep_range(reg->delay, reg->delay + 10);
reg++;