diff options
| author | Arun KS <arunks@codeaurora.org> | 2017-09-12 15:16:01 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-09-13 22:05:08 -0700 |
| commit | 972d901c7c6da792f13373c9079ab2d6e2df5e1d (patch) | |
| tree | 73ff5060e29cdfe1f7e7283eee31a3b9444f2fdd /drivers/soc | |
| parent | 414269dd957a220c48ca82cb3364412f50d18c98 (diff) | |
soc: qcom: pil: set device dma mask as 32 bit
APPS interact with MPSS through 32 bit register interface.
Set dma mask for 32 bit so that mba and mdt memory are allocated
from 32 bit physical address range.
Change-Id: I623f00097d464b1bdd8f609e2d6c9a126f4bea4d
Signed-off-by: Arun KS <arunks@codeaurora.org>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/qcom/pil-msa.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/soc/qcom/pil-msa.c b/drivers/soc/qcom/pil-msa.c index 4bea034f0bdd..60d0f2a37026 100644 --- a/drivers/soc/qcom/pil-msa.c +++ b/drivers/soc/qcom/pil-msa.c @@ -583,7 +583,7 @@ int pil_mss_reset_load_mba(struct pil_desc *pil) arch_setup_dma_ops(dma_dev, 0, 0, NULL, 0); - dma_dev->coherent_dma_mask = DMA_BIT_MASK(sizeof(dma_addr_t) * 8); + dma_dev->coherent_dma_mask = DMA_BIT_MASK(32); init_dma_attrs(&md->attrs_dma); dma_set_attr(DMA_ATTR_SKIP_ZEROING, &md->attrs_dma); @@ -695,7 +695,7 @@ static int pil_msa_auth_modem_mdt(struct pil_desc *pil, const u8 *metadata, trace_pil_func(__func__); - dma_dev->coherent_dma_mask = DMA_BIT_MASK(sizeof(dma_addr_t) * 8); + dma_dev->coherent_dma_mask = DMA_BIT_MASK(32); dma_set_attr(DMA_ATTR_SKIP_ZEROING, &attrs); dma_set_attr(DMA_ATTR_STRONGLY_ORDERED, &attrs); /* Make metadata physically contiguous and 4K aligned. */ |