diff options
| author | Yan He <yanhe@codeaurora.org> | 2015-05-29 13:43:31 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:16:07 -0700 |
| commit | a0ad90f548fa9e562053d05b6875fe425eb1869d (patch) | |
| tree | f8718d6ccddb3bbe31a0b60d7e35d256fc1777ed /drivers/platform | |
| parent | 3e255410ad3d56e1365d82dd14ae965ddad80c98 (diff) | |
msm: ep_pcie: update read-only registers for compliance testing
Update some read-only PCIe registers with non-arbitrary values
which are required by PCIe compliance testing.
Change-Id: I10fd448f38d874ba582d1a46a98a76d29e0d9cb4
Signed-off-by: Yan He <yanhe@codeaurora.org>
Diffstat (limited to 'drivers/platform')
| -rw-r--r-- | drivers/platform/msm/ep_pcie/ep_pcie_com.h | 1 | ||||
| -rw-r--r-- | drivers/platform/msm/ep_pcie/ep_pcie_core.c | 9 |
2 files changed, 8 insertions, 2 deletions
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h index 91566446f401..6c4d69a2d459 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h +++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h @@ -53,6 +53,7 @@ #define PCIE20_CLASS_CODE_REVISION_ID 0x08 #define PCIE20_BIST_HDR_TYPE 0x0C #define PCIE20_BAR0 0x10 +#define PCIE20_SUBSYSTEM 0x2c #define PCIE20_CAP_ID_NXT_PTR 0x40 #define PCIE20_CON_STATUS 0x44 #define PCIE20_MSI_CAP_ID_NEXT_CTRL 0x50 diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index ccca861a8180..2a646c166d7f 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -439,15 +439,17 @@ static void ep_pcie_bar_init(struct ep_pcie_dev_t *dev) /* Configure BAR mask via CS2 */ ep_pcie_write_mask(dev->elbi + PCIE20_ELBI_CS2_ENABLE, 0, BIT(0)); ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0, mask); + ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x4, 0); ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x8, mask); - ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x10, mask); + ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0xc, 0); + ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x10, 0); + ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x14, 0); ep_pcie_write_mask(dev->elbi + PCIE20_ELBI_CS2_ENABLE, BIT(0), 0); /* Configure BAR properties via CS */ ep_pcie_write_mask(dev->dm_core + PCIE20_MISC_CONTROL_1, 0, BIT(0)); ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0, properties); ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x8, properties); - ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x10, properties); ep_pcie_write_mask(dev->dm_core + PCIE20_MISC_CONTROL_1, BIT(0), 0); } @@ -508,6 +510,9 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev) /* Set header type */ ep_pcie_write_reg(dev->dm_core, PCIE20_BIST_HDR_TYPE, 0x10); + /* Set Subsystem ID and Subsystem Vendor ID */ + ep_pcie_write_reg(dev->dm_core, PCIE20_SUBSYSTEM, 0xa01f17cb); + /* Set the PMC Register - to support PME in D0, D3hot and D3cold */ ep_pcie_write_mask(dev->dm_core + PCIE20_CAP_ID_NXT_PTR, 0, BIT(31)|BIT(30)|BIT(27)); |