diff options
| author | Subhash Jadavani <subhashj@codeaurora.org> | 2015-02-05 13:40:09 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:01:16 -0700 |
| commit | 9afc3bb60a4e87b86779ce224d51bd4aa11cb0e6 (patch) | |
| tree | 9753fd5510a4594a18f41e86ae5851f06e34ad75 /drivers/phy | |
| parent | dcaa49102159b495b7a62cd4952789cbaa9dd03d (diff) | |
phy: qcom-ufs-qmp-14nm: update PHY power up sequence
Hardware programming guide recommends one more PHY setting as part
of UFS PHY power up sequence hence this change adds it.
Change-Id: I92f77faa6ca28d6f72d7601344b439ef7596d572
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/phy-qcom-ufs-qmp-14nm.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/phy/phy-qcom-ufs-qmp-14nm.h b/drivers/phy/phy-qcom-ufs-qmp-14nm.h index 8d53da576041..41397bea5f0e 100644 --- a/drivers/phy/phy-qcom-ufs-qmp-14nm.h +++ b/drivers/phy/phy-qcom-ufs-qmp-14nm.h @@ -78,6 +78,7 @@ #define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x1A8) #define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x1AC) #define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x1B0) +#define QSERDES_COM_CMN_MISC2 COM_OFF(0x1B8) #define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x1BC) /* UFS PHY registers */ @@ -184,6 +185,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_0_0[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESCODE_DIV_NUM, 0x15), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MISC2, 0x1F), /* * UFS_PHY_RX_PWM_GEAR_BAND configuration is changed after the power up * sequence so make sure that this register gets set to power on reset |