diff options
| author | Maya Erez <merez@codeaurora.org> | 2016-02-28 09:52:25 +0200 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 19:58:09 -0700 |
| commit | cd958296acba6ce3e0d63198cae64d1b8d03dfcf (patch) | |
| tree | 38274fbe6a8cfae10367f5103ef35627d1b170db /drivers/net/wireless/ath | |
| parent | faab237c9c73dbca5e7c6fa35808eb2ac11bcbf8 (diff) | |
wil6210: enable WA for PCIe HW errata
WA for HW errata for PCIe in MSM8998 v1, QCTDD02664351.
Due to this issue, PCIe write ordering rule may be violated
causing cluster to read older data from its L2 cache, in specific
scenario.
To avoid that for wil6210 rx transactions, we set "no snoop" for
PCIe wr transactions (from device to host).
For configuring the above bit 4 of 0x8812C4 register is set.
Signed-off-by: Maya Erez <merez@codeaurora.org>
Diffstat (limited to 'drivers/net/wireless/ath')
| -rw-r--r-- | drivers/net/wireless/ath/wil6210/main.c | 4 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/wil6210/wil6210.h | 3 |
2 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/wil6210/main.c b/drivers/net/wireless/ath/wil6210/main.c index 0652efed6b5d..26606ef49d61 100644 --- a/drivers/net/wireless/ath/wil6210/main.c +++ b/drivers/net/wireless/ath/wil6210/main.c @@ -621,6 +621,10 @@ static int wil_target_reset(struct wil6210_priv *wil) wil_s(wil, RGF_DMA_OFUL_NID_0, BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN | BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC); + /* Enable fix for PCIe HW bug, set "No snoop" for RX transactions */ + wil_s(wil, RGF_DMA_PEDI_DIF, BIT_DMA_WR_CMD_ATTR_NO_SNOOP | + BIT_DMA_WR_CMD_ATTR_RELAXED_ORDERING); + wil_dbg_misc(wil, "Reset completed in %d ms\n", delay * RST_DELAY); return 0; } diff --git a/drivers/net/wireless/ath/wil6210/wil6210.h b/drivers/net/wireless/ath/wil6210/wil6210.h index 1b8fa1d2bae9..e07ce3832c27 100644 --- a/drivers/net/wireless/ath/wil6210/wil6210.h +++ b/drivers/net/wireless/ath/wil6210/wil6210.h @@ -156,6 +156,9 @@ struct RGF_ICR { #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) +#define RGF_DMA_PEDI_DIF (0x8812C4) /* struct RGF_PEDI_DIF */ + #define BIT_DMA_WR_CMD_ATTR_NO_SNOOP BIT(4) + #define BIT_DMA_WR_CMD_ATTR_RELAXED_ORDERING BIT(5) #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ |