diff options
| author | Veerabhadrarao Badiganti <vbadigan@codeaurora.org> | 2017-01-31 07:33:29 +0530 |
|---|---|---|
| committer | Veerabhadrarao Badiganti <vbadigan@codeaurora.org> | 2017-02-02 06:35:34 +0530 |
| commit | bd4fadcb01db6e370cc60953575b3ecee6b4bf50 (patch) | |
| tree | 653b81e7ffaa7aba7598feb54dde004178f704b8 /drivers/mmc | |
| parent | af883d4db0b398542bb561808a11019f0998d129 (diff) | |
mmc: sdhci-msm-ice: Factor out update config from sdhci_msm_ice_cfg
Factor out the logic of updating the SDHC ICE config registers
from sdhci_msm_ice_cfg().
For ICE3.0, different set of SDHC ICE registers are need to be updated.
So having this logic in separate functions, we can have logical
separation for ICE2.0 and ICE3.0.
Change-Id: Ib3d3f9701875000985dc9382bdcdf5fb0e872a43
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sdhci-msm-ice.c | 62 |
1 files changed, 35 insertions, 27 deletions
diff --git a/drivers/mmc/host/sdhci-msm-ice.c b/drivers/mmc/host/sdhci-msm-ice.c index dc8d865cfabc..acc4ae089e39 100644 --- a/drivers/mmc/host/sdhci-msm-ice.c +++ b/drivers/mmc/host/sdhci-msm-ice.c @@ -211,6 +211,39 @@ void sdhci_msm_ice_cfg_reset(struct sdhci_host *host, u32 slot) host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_3_n + 16 * slot); } +static +void sdhci_msm_ice_update_cfg(struct sdhci_host *host, u64 lba, + u32 slot, unsigned int bypass, short key_index) +{ + unsigned int ctrl_info_val = 0; + + /* Configure ICE index */ + ctrl_info_val = + (key_index & + MASK_SDHCI_MSM_ICE_CTRL_INFO_KEY_INDEX) + << OFFSET_SDHCI_MSM_ICE_CTRL_INFO_KEY_INDEX; + + /* Configure data unit size of transfer request */ + ctrl_info_val |= + (SDHCI_MSM_ICE_TR_DATA_UNIT_512_B & + MASK_SDHCI_MSM_ICE_CTRL_INFO_CDU) + << OFFSET_SDHCI_MSM_ICE_CTRL_INFO_CDU; + + /* Configure ICE bypass mode */ + ctrl_info_val |= + (bypass & MASK_SDHCI_MSM_ICE_CTRL_INFO_BYPASS) + << OFFSET_SDHCI_MSM_ICE_CTRL_INFO_BYPASS; + + writel_relaxed((lba & 0xFFFFFFFF), + host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_1_n + 16 * slot); + writel_relaxed(((lba >> 32) & 0xFFFFFFFF), + host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_2_n + 16 * slot); + writel_relaxed(ctrl_info_val, + host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_3_n + 16 * slot); + /* Ensure ICE registers are configured before issuing SDHCI request */ + mb(); +} + int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *mrq, u32 slot) { @@ -219,7 +252,6 @@ int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *mrq, int err = 0; struct ice_data_setting ice_set; sector_t lba = 0; - unsigned int ctrl_info_val = 0; unsigned int bypass = SDHCI_MSM_ICE_ENABLE_BYPASS; struct request *req; @@ -262,32 +294,8 @@ int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *mrq, ice_set.crypto_data.key_index); } - /* Configure ICE index */ - ctrl_info_val = - (ice_set.crypto_data.key_index & - MASK_SDHCI_MSM_ICE_CTRL_INFO_KEY_INDEX) - << OFFSET_SDHCI_MSM_ICE_CTRL_INFO_KEY_INDEX; - - /* Configure data unit size of transfer request */ - ctrl_info_val |= - (SDHCI_MSM_ICE_TR_DATA_UNIT_512_B & - MASK_SDHCI_MSM_ICE_CTRL_INFO_CDU) - << OFFSET_SDHCI_MSM_ICE_CTRL_INFO_CDU; - - /* Configure ICE bypass mode */ - ctrl_info_val |= - (bypass & MASK_SDHCI_MSM_ICE_CTRL_INFO_BYPASS) - << OFFSET_SDHCI_MSM_ICE_CTRL_INFO_BYPASS; - - writel_relaxed((lba & 0xFFFFFFFF), - host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_1_n + 16 * slot); - writel_relaxed(((lba >> 32) & 0xFFFFFFFF), - host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_2_n + 16 * slot); - writel_relaxed(ctrl_info_val, - host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL_INFO_3_n + 16 * slot); - - /* Ensure ICE registers are configured before issuing SDHCI request */ - mb(); + sdhci_msm_ice_update_cfg(host, lba, slot, bypass, + ice_set.crypto_data.key_index); return 0; } |