diff options
| author | Sahitya Tummala <stummala@codeaurora.org> | 2015-03-03 14:03:20 +0530 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-31 15:27:18 -0700 |
| commit | b0a69fc74bd014dc8109a0dfeab58233d793ceb1 (patch) | |
| tree | 349fcf11e25ea9a2882bcf558e2b87b3b5d0f4d2 /drivers/mmc | |
| parent | d397fec7fec5e6ead7dd3e54f48faca88aa71cf5 (diff) | |
mmc: sdhci-msm: Enable one MID for SDHCI controller
The SDHCI reset for data is getting stuck with the default
MID configuration which uses descriptor requests with MID=0
and data requests with MID=1. This enables interleaving
between MID and is causing reset to be stuck somewhere in the
path DDR<->NOC<->SDHC on few chipsets. Enable one MID mode
as a workaround to this problem which is observed on SDCC5
controller of 8916/8939 and 8992 chipsets.
Change-Id: I12343b35d45774668b7e823ccaa067813fcea4cf
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sdhci-msm.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index c897cacce14a..e194a2ad55ad 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -118,6 +118,9 @@ #define CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 0x114 #define CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 0x118 +#define CORE_VENDOR_SPEC_FUNC2 0x110 +#define CORE_ONE_MID_EN (1 << 25) + #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11C #define CORE_8_BIT_SUPPORT (1 << 18) #define CORE_3_3V_SUPPORT (1 << 24) @@ -2820,6 +2823,8 @@ void sdhci_msm_dump_vendor_regs(struct sdhci_host *host) readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC), readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR0), readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR1)); + pr_info("Vndr func2: 0x%08x\n", + readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_FUNC2)); /* * tbsel indicates [2:0] bits and tbsel2 indicates [7:4] bits @@ -2977,6 +2982,7 @@ static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host, u32 version, caps = 0; u16 minor; u8 major; + u32 val; version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION); major = (version & CORE_VERSION_MAJOR_MASK) >> @@ -3006,6 +3012,15 @@ static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host, } /* + * Enable one MID mode for SDCC5 (major 1) on 8916/8939 (minor 0x2e) and + * on 8992 (minor 0x3e) as a workaround to reset for data stuck issue. + */ + if (major == 1 && (minor == 0x2e || minor == 0x3e)) { + val = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_FUNC2); + writel_relaxed((val | CORE_ONE_MID_EN), + host->ioaddr + CORE_VENDOR_SPEC_FUNC2); + } + /* * SDCC 5 controller with major version 1, minor version 0x34 and later * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL. */ |