diff options
| author | Venkat Gopalakrishnan <venkatg@codeaurora.org> | 2015-06-24 14:46:49 -0700 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-31 15:26:45 -0700 |
| commit | 77bb196cf5a4afea007794716e41f4b4c303856e (patch) | |
| tree | e58de16f4c628c4573c3e917a3d38f6adc091c63 /drivers/mmc | |
| parent | 7f8ab6548b20d17c4c4c0212ea8e5ccfcf902ad8 (diff) | |
mmc: sdhci-msm: Reset vendor specific func register on probe
The vendor specific func register doesn't get reset when using the
software reset register. The various bootloader's could leave this
in an unknown state, hence reset this register to it's power on reset
value during probe.
Change-Id: I3258eedf87b1bc945f43b85627948e6c92b74686
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sdhci-msm.c | 22 |
1 files changed, 5 insertions, 17 deletions
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 4d2ba991285d..33cb44a36a5f 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -113,6 +113,7 @@ #define CORE_HC_SELECT_IN_EN (1 << 18) #define CORE_HC_SELECT_IN_HS400 (6 << 19) #define CORE_HC_SELECT_IN_MASK (7 << 19) +#define CORE_VENDOR_SPEC_POR_VAL 0xA1C #define CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 0x114 #define CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 0x118 @@ -2886,7 +2887,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) struct resource *core_memres = NULL; int ret = 0, dead = 0; u16 host_version; - u32 pwr, irq_status, irq_ctl; + u32 irq_status, irq_ctl; pr_debug("%s: Enter %s\n", dev_name(&pdev->dev), __func__); msm_host = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_msm_host), @@ -3074,25 +3075,12 @@ static int sdhci_msm_probe(struct platform_device *pdev) goto vreg_deinit; } - /* Unset HC_MODE_EN bit in HC_MODE register */ - writel_relaxed(0, (msm_host->core_mem + CORE_HC_MODE)); - - /* Set SW_RST bit in POWER register (Offset 0x0) */ - writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | - CORE_SW_RST, msm_host->core_mem + CORE_POWER); /* - * SW reset can take upto 10HCLK + 15MCLK cycles. - * Calculating based on min clk rates (hclk = 27MHz, - * mclk = 400KHz) it comes to ~40us. Let's poll for - * max. 1ms for reset completion. + * Reset the vendor spec register to power on reset state. */ - ret = readl_poll_timeout(msm_host->core_mem + CORE_POWER, - pwr, !(pwr & CORE_SW_RST), 10, 1000); + writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, + host->ioaddr + CORE_VENDOR_SPEC); - if (ret) { - dev_err(&pdev->dev, "reset failed (%d)\n", ret); - goto vreg_deinit; - } /* Set HC_MODE_EN bit in HC_MODE register */ writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); |