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| author | Vincent Whitchurch <vincent.whitchurch@axis.com> | 2021-06-30 12:22:32 +0200 |
|---|---|---|
| committer | Sasha Levin <sashal@kernel.org> | 2021-08-26 08:37:52 -0400 |
| commit | 61eb2ee2c46b8e128489443fa3fd6d18669e0e1e (patch) | |
| tree | 1c97ae5d5ebc637bbf21029c150ec52c40dfff0c /drivers/misc/ibmasm/module.c | |
| parent | 613612a2ef1e1614eca90f590417ceecf5211699 (diff) | |
mmc: dw_mmc: Fix hang on data CRC error
[ Upstream commit 25f8203b4be1937c4939bb98623e67dcfd7da4d1 ]
When a Data CRC interrupt is received, the driver disables the DMA, then
sends the stop/abort command and then waits for Data Transfer Over.
However, sometimes, when a data CRC error is received in the middle of a
multi-block write transfer, the Data Transfer Over interrupt is never
received, and the driver hangs and never completes the request.
The driver sets the BMOD.SWR bit (SDMMC_IDMAC_SWRESET) when stopping the
DMA, but according to the manual CMD.STOP_ABORT_CMD should be programmed
"before assertion of SWR". Do these operations in the recommended
order. With this change the Data Transfer Over is always received
correctly in my tests.
Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20210630102232.16011-1-vincent.whitchurch@axis.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/misc/ibmasm/module.c')
0 files changed, 0 insertions, 0 deletions
