diff options
| author | Vijay kumar Tumati <vtumati@codeaurora.org> | 2018-03-08 22:14:25 +0530 |
|---|---|---|
| committer | Vijay kumar Tumati <vtumati@codeaurora.org> | 2018-04-20 12:30:58 +0530 |
| commit | 28b773c49cfe72c46a22bb5cf8dbb6806b5ef181 (patch) | |
| tree | b347e9a378086b69dae11ba80d20ebce2ad8f165 /drivers/media | |
| parent | 169e423524f3fdcce14d614e714c5192ca6a21f2 (diff) | |
msm: camera: sensor: Program SDR mask delay based on data rate
Program camera csiphy correctly by using sensor output data rate
information.
Change-Id: I34f4b6b88f645aa620c4d03be2d7905c0951fd4e
Signed-off-by: Vijay kumar Tumati <vtumati@codeaurora.org>
Diffstat (limited to 'drivers/media')
| -rw-r--r-- | drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c index 30abd683118e..5fc2aed87e19 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c @@ -52,6 +52,7 @@ #define MAX_DPHY_DATA_LN 4 #define CLOCK_OFFSET 0x700 #define CSIPHY_SOF_DEBUG_COUNT 2 +#define GBPS 1000000000 #undef CDBG #define CDBG(fmt, args...) pr_debug(fmt, ##args) @@ -281,11 +282,20 @@ static int msm_csiphy_3phase_lane_config( csiphy_3ph_reg.mipi_csiphy_3ph_lnn_ctrl51.addr + 0x200*i); } - msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg. - mipi_csiphy_3ph_lnn_ctrl25.data, - csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg. - mipi_csiphy_3ph_lnn_ctrl25.addr + 0x200*i); - + if ((csiphy_dev->hw_version == CSIPHY_VERSION_V35) && + ((csiphy_params->data_rate / + csiphy_params->lane_cnt) > 2 * GBPS)) { + msm_camera_io_w(0x40, + csiphybase + + csiphy_dev->ctrl_reg->csiphy_3ph_reg. + mipi_csiphy_3ph_lnn_ctrl25.addr + 0x200*i); + } else { + msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg. + mipi_csiphy_3ph_lnn_ctrl25.data, + csiphybase + + csiphy_dev->ctrl_reg->csiphy_3ph_reg. + mipi_csiphy_3ph_lnn_ctrl25.addr + 0x200*i); + } lane_mask >>= 1; i++; } |