diff options
| author | Harshdeep Dhatt <hdhatt@codeaurora.org> | 2016-07-07 10:48:24 -0600 |
|---|---|---|
| committer | Harshdeep Dhatt <hdhatt@codeaurora.org> | 2016-09-23 10:08:21 -0600 |
| commit | da71b33976eade0dc55b231e318b5361bd65b7f1 (patch) | |
| tree | fbc655bd2df96c0c0a34740f89100b272e0836c8 /drivers/gpu | |
| parent | 9e2d528dc47d04e98c5e6f1c4ef84fc268115d36 (diff) | |
msm: kgsl: Disable rbbm countable on a540
The RBBM_ALWAYS_COUNT countable does not function properly
when top level clock gating is enabled. Return -EINVAL
when user requests this perfcounter.
CRs-Fixed: 1038778
Change-Id: I48d560ab2caa6ea467ac56bf0d323937a475cdde
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/msm/a5xx_reg.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/msm/adreno_perfcounter.c | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/msm/a5xx_reg.h b/drivers/gpu/msm/a5xx_reg.h index cedd02987002..3b29452ce8bd 100644 --- a/drivers/gpu/msm/a5xx_reg.h +++ b/drivers/gpu/msm/a5xx_reg.h @@ -788,6 +788,9 @@ /* COUNTABLE FOR TSE PERFCOUNTER */ #define A5XX_TSE_INPUT_PRIM_NUM 0x6 +/* COUNTABLE FOR RBBM PERFCOUNTER */ +#define A5XX_RBBM_ALWAYS_COUNT 0x0 + /* GPMU POWER COUNTERS */ #define A5XX_SP_POWER_COUNTER_0_LO 0xA840 #define A5XX_SP_POWER_COUNTER_0_HI 0xA841 diff --git a/drivers/gpu/msm/adreno_perfcounter.c b/drivers/gpu/msm/adreno_perfcounter.c index 10f4577c1103..8e354d71a291 100644 --- a/drivers/gpu/msm/adreno_perfcounter.c +++ b/drivers/gpu/msm/adreno_perfcounter.c @@ -812,6 +812,11 @@ static int adreno_perfcounter_enable(struct adreno_device *adreno_dev, case KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR: _power_counter_enable_alwayson(adreno_dev, counters); break; + case KGSL_PERFCOUNTER_GROUP_RBBM: + /* The following rbbm countable is not reliable on a540 */ + if (adreno_is_a540(adreno_dev)) + if (countable == A5XX_RBBM_ALWAYS_COUNT) + return -EINVAL; default: return _perfcounter_enable_default(adreno_dev, counters, group, counter, countable); |