msm: kgsl: Create sysfs entry to control GPU clock throttling.

Create sysfs entry to control GPU clock throttling. When 0 is
written - all sources of clock throlling - ie LM, BCL, IDLE
are disabled.

CRs-Fixed: 973565
Change-Id: Iad588eb94861bd6b223715cc05354e3c39db9b24
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>

5 files changed, 23 insertions, 1 deletions

diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 36c336a0477e..b9a379bdc5a5 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -97,7 +97,8 @@ static struct adreno_device device_3d0 = {
 	.input_work = __WORK_INITIALIZER(device_3d0.input_work,
 		adreno_input_work),
 	.pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) | BIT(ADRENO_PPD_CTRL) |
-		BIT(ADRENO_LM_CTRL) | BIT(ADRENO_HWCG_CTRL),
+		BIT(ADRENO_LM_CTRL) | BIT(ADRENO_HWCG_CTRL) |
+		BIT(ADRENO_THROTTLING_CTRL),
 	.profile.enabled = false,
 	.active_list = LIST_HEAD_INIT(device_3d0.active_list),
 	.active_list_lock = __SPIN_LOCK_UNLOCKED(device_3d0.active_list_lock),
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index b8029178f932..7ac91f203a70 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -183,6 +183,8 @@ enum adreno_gpurev {
 #define ADRENO_PPD_CTRL     1
 #define ADRENO_LM_CTRL      2
 #define ADRENO_HWCG_CTRL    3
+#define ADRENO_THROTTLING_CTRL 4
+
 
 /* number of throttle counters for DCVS adjustment */
 #define ADRENO_GPMU_THROTTLE_COUNTERS 4
diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c
index b34e8f6ae433..5fb912738796 100644
--- a/drivers/gpu/msm/adreno_a5xx.c
+++ b/drivers/gpu/msm/adreno_a5xx.c
@@ -1853,6 +1853,9 @@ static void a540_lm_init(struct adreno_device *adreno_dev)
 		<< AGC_GPU_VERSION_SHIFT);
 	unsigned int r, i;
 
+	if (!test_bit(ADRENO_THROTTLING_CTRL, &adreno_dev->pwrctrl_flag))
+		agc_lm_config |= AGC_THROTTLE_DISABLE;
+
 	if (lm_on(adreno_dev)) {
 		agc_lm_config |=
 			AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE |
diff --git a/drivers/gpu/msm/adreno_a5xx.h b/drivers/gpu/msm/adreno_a5xx.h
index e4b099aa30d1..1174ea68287f 100644
--- a/drivers/gpu/msm/adreno_a5xx.h
+++ b/drivers/gpu/msm/adreno_a5xx.h
@@ -194,6 +194,8 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);
 #define AGC_LM_CONFIG_ENABLE_ERROR	(3 << 4)
 
 #define AGC_THROTTLE_SEL_DCS		(1 << 8)
+#define AGC_THROTTLE_DISABLE            (2 << 8)
+
 
 #define AGC_LLM_ENABLED			(1 << 16)
 #define	AGC_GPU_VERSION_MASK		GENMASK(18, 17)
diff --git a/drivers/gpu/msm/adreno_sysfs.c b/drivers/gpu/msm/adreno_sysfs.c
index f9d16222177c..f893b29e816e 100644
--- a/drivers/gpu/msm/adreno_sysfs.c
+++ b/drivers/gpu/msm/adreno_sysfs.c
@@ -201,6 +201,17 @@ static unsigned int _hwcg_show(struct adreno_device *adreno_dev)
 	return test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag);
 }
 
+static int _throttling_store(struct adreno_device *adreno_dev,
+	unsigned int val)
+{
+	 return _pwrctrl_store(adreno_dev, val, ADRENO_THROTTLING_CTRL);
+}
+
+static unsigned int _throttling_show(struct adreno_device *adreno_dev)
+{
+	return test_bit(ADRENO_THROTTLING_CTRL, &adreno_dev->pwrctrl_flag);
+}
+
 static int _sptp_pc_store(struct adreno_device *adreno_dev,
 		unsigned int val)
 {
@@ -315,6 +326,8 @@ static ADRENO_SYSFS_BOOL(sptp_pc);
 static ADRENO_SYSFS_BOOL(lm);
 static ADRENO_SYSFS_BOOL(preemption);
 static ADRENO_SYSFS_BOOL(hwcg);
+static ADRENO_SYSFS_BOOL(throttling);
+
 
 
 static const struct device_attribute *_attr_list[] = {
@@ -329,6 +342,7 @@ static const struct device_attribute *_attr_list[] = {
 	&adreno_attr_lm.attr,
 	&adreno_attr_preemption.attr,
 	&adreno_attr_hwcg.attr,
+	&adreno_attr_throttling.attr,
 	NULL,
 };