Merge "drm: msm: sde: reduce black screen duration from null commit"

5 files changed, 73 insertions, 26 deletions

diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_shd.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_shd.c
index 2eb25e9d38f0..5ba2035d389b 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_shd.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_shd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -311,7 +311,8 @@ end:
 }
 
 static void _sde_shd_hw_ctl_clear_all_blendstages(struct sde_hw_ctl *ctx,
-	bool handoff, const u32 *resv_pipes, u32 resv_pipes_length)
+	bool handoff, const struct splash_reserved_pipe_info *resv_pipes,
+	u32 resv_pipes_length)
 {
 	struct sde_shd_hw_ctl *hw_ctl;
 	int i;
@@ -345,7 +346,8 @@ static inline int _stage_offset(struct sde_hw_mixer *ctx, enum sde_stage stage)
 
 static void _sde_shd_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
 	enum sde_lm lm, struct sde_hw_stage_cfg *stage_cfg, u32 index,
-	bool handoff, const u32 *resv_pipes, u32 resv_pipes_length)
+	bool handoff, const struct splash_reserved_pipe_info *resv_pipes,
+	u32 resv_pipes_length)
 {
 	struct sde_shd_hw_ctl *hw_ctl;
 	u32 mixercfg = 0, mixercfg_ext = 0, mix, ext, full, mixercfg_ext2;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ctl.c b/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
index 8b5d8614f7ec..6ed424217183 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
@@ -258,8 +258,9 @@ static inline int sde_hw_ctl_get_bitmask_cdm(struct sde_hw_ctl *ctx,
 	return 0;
 }
 
-static inline void sde_hw_ctl_get_splash_mixer_mask(const u32 *resv_pipes,
-				u32 length, u32 *mixercfg, u32 *mixercfg_ext)
+static inline void sde_hw_ctl_get_splash_mixer_mask(
+			const struct splash_reserved_pipe_info *resv_pipes,
+			u32 length, u32 *mixercfg, u32 *mixercfg_ext)
 {
 	int i = 0;
 	u32 mixer_mask = 0;
@@ -268,7 +269,7 @@ static inline void sde_hw_ctl_get_splash_mixer_mask(const u32 *resv_pipes,
 	for (i = 0; i < length; i++) {
 		/* LK's splash VIG layer always stays on second top */
 		/*  most layerearly HMI RGB layer stays at top most layer */
-		switch (resv_pipes[i]) {
+		switch (resv_pipes[i].pipe_id) {
 		case SSPP_VIG0:
 			mixer_mask |= 0x7 << 0;
 			mixer_ext_mask |= BIT(0);
@@ -285,20 +286,25 @@ static inline void sde_hw_ctl_get_splash_mixer_mask(const u32 *resv_pipes,
 			mixer_mask |= 0x7 << 26;
 			mixer_ext_mask |= BIT(6);
 			break;
+		/*
+		 * If going here, that means the call comes from one
+		 * NULL commit, so stage RGB pipe as the same stage level
+		 * as that in bootloader splash.
+		 */
 		case SSPP_RGB0:
-			mixer_mask |= 0x7 << 9;
+			mixer_mask |= 0x2 << 9;
 			mixer_ext_mask |= BIT(8);
 			break;
 		case SSPP_RGB1:
-			mixer_mask |= 0x7 << 12;
+			mixer_mask |= 0x2 << 12;
 			mixer_ext_mask |= BIT(10);
 			break;
 		case SSPP_RGB2:
-			mixer_mask |= 0x7 << 15;
+			mixer_mask |= 0x2 << 15;
 			mixer_ext_mask |= BIT(12);
 			break;
 		case SSPP_RGB3:
-			mixer_mask |= 0x7 << 29;
+			mixer_mask |= 0x2 << 29;
 			mixer_ext_mask |= BIT(14);
 			break;
 		default:
@@ -364,7 +370,9 @@ static int sde_hw_ctl_wait_reset_status(struct sde_hw_ctl *ctx)
 }
 
 static void sde_hw_ctl_clear_all_blendstages(struct sde_hw_ctl *ctx,
-		bool handoff, const u32 *resv_pipes, u32 resv_pipes_length)
+	bool handoff,
+	const struct splash_reserved_pipe_info *resv_pipes,
+	u32 resv_pipes_length)
 {
 	struct sde_hw_blk_reg_map *c = &ctx->hw;
 	int i;
@@ -402,7 +410,9 @@ static void sde_hw_ctl_clear_all_blendstages(struct sde_hw_ctl *ctx,
 
 static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
 	enum sde_lm lm, struct sde_hw_stage_cfg *stage_cfg, u32 index,
-	bool handoff, const u32 *resv_pipes, u32 resv_pipes_length)
+	bool handoff,
+	const struct splash_reserved_pipe_info *resv_pipes,
+	u32 resv_pipes_length)
 {
 	struct sde_hw_blk_reg_map *c = &ctx->hw;
 	u32 mixercfg, mixercfg_ext, mix, ext, mixercfg_ext2;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ctl.h b/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
index 5538c807692c..ef4ddfafa566 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
@@ -16,6 +16,7 @@
 #include "sde_hw_mdss.h"
 #include "sde_hw_util.h"
 #include "sde_hw_catalog.h"
+#include "sde_splash.h"
 
 /**
  * sde_ctl_mode_sel: Interface mode selection
@@ -148,10 +149,12 @@ struct sde_hw_ctl_ops {
 	 * @ctx       : ctl path ctx pointer
 	 * @handoff   : indicate if lk is prepare for handoff
 	 * @resv_pipes  : reserved pipes in DT
-	 * @resv_pipes_length:    array size of array reserved_pipes
+	 * @resv_pipes_length: array size of array reserved_pipes
 	 */
 	void (*clear_all_blendstages)(struct sde_hw_ctl *ctx,
-		bool handoff, const u32 *resv_pipes, u32 resv_pipes_length);
+		bool handoff,
+		const struct splash_reserved_pipe_info *resv_pipes,
+		u32 resv_pipes_length);
 
 	/**
 	 * Configure layer mixer to pipe configuration
@@ -160,11 +163,13 @@ struct sde_hw_ctl_ops {
 	 * @cfg       : blend stage configuration
 	 * @handoff   : indicate if lk is prepare for handoff
 	 * @resv_pipes  : reserved pipes in DT
-	 * @resv_pipes_length:   array size of array reserved_pipes
+	 * @resv_pipes_length: array size of array reserved_pipes
 	 */
 	void (*setup_blendstage)(struct sde_hw_ctl *ctx,
 		enum sde_lm lm, struct sde_hw_stage_cfg *cfg, u32 index,
-		bool handoff, const u32 *resv_pipes, u32 resv_pipes_length);
+		bool handoff,
+		const struct splash_reserved_pipe_info *resv_pipes,
+		u32 resv_pipes_length);
 
 	/**
 	 * read CTL_TOP register value for splash case
diff --git a/drivers/gpu/drm/msm/sde/sde_splash.c b/drivers/gpu/drm/msm/sde/sde_splash.c
index 2b9a070db0fe..9ef924ccc557 100644
--- a/drivers/gpu/drm/msm/sde/sde_splash.c
+++ b/drivers/gpu/drm/msm/sde/sde_splash.c
@@ -306,9 +306,10 @@ static void _sde_splash_sent_pipe_update_uevent(struct sde_kms *sde_kms)
 	}
 
 	for (i = 0; i < MAX_BLOCKS; i++) {
-		if (sde_kms->splash_info.reserved_pipe_info[i] != 0xFFFFFFFF)
+		if (sde_kms->splash_info.reserved_pipe_info[i].pipe_id !=
+								0xFFFFFFFF)
 			snprintf(event_string, SZ_4K, "pipe%d avialable",
-				sde_kms->splash_info.reserved_pipe_info[i]);
+			sde_kms->splash_info.reserved_pipe_info[i].pipe_id);
 	}
 
 	DRM_INFO("generating pipe update event[%s]", event_string);
@@ -401,6 +402,21 @@ static void _sde_splash_update_property(struct sde_kms *sde_kms)
 					catalog->max_mixer_blendstages);
 }
 
+static void
+_sde_splash_release_early_splash_layer(struct sde_splash_info *splash_info)
+{
+	int i = 0;
+
+	for (i = 0; i < MAX_BLOCKS; i++) {
+		if (splash_info->reserved_pipe_info[i].early_release) {
+			splash_info->reserved_pipe_info[i].pipe_id =
+								0xFFFFFFFF;
+			splash_info->reserved_pipe_info[i].early_release =
+								false;
+		}
+	}
+}
+
 __ref int sde_splash_init(struct sde_power_handle *phandle, struct msm_kms *kms)
 {
 	struct sde_kms *sde_kms;
@@ -522,8 +538,10 @@ int sde_splash_parse_reserved_plane_dt(struct drm_device *dev,
 	if (!parent)
 		return -EINVAL;
 
-	for (i = 0; i < MAX_BLOCKS; i++)
-		splash_info->reserved_pipe_info[i] = 0xFFFFFFFF;
+	for (i = 0; i < MAX_BLOCKS; i++) {
+		splash_info->reserved_pipe_info[i].pipe_id = 0xFFFFFFFF;
+		splash_info->reserved_pipe_info[i].early_release = false;
+	}
 
 	i = 0;
 	for_each_child_of_node(parent, node) {
@@ -536,8 +554,11 @@ int sde_splash_parse_reserved_plane_dt(struct drm_device *dev,
 
 		of_property_for_each_string(node, "qcom,plane-name",
 					prop, cname)
-		splash_info->reserved_pipe_info[i] =
+			splash_info->reserved_pipe_info[i].pipe_id =
 					_sde_splash_parse_sspp_id(cfg, cname);
+
+		splash_info->reserved_pipe_info[i].early_release =
+			of_property_read_bool(node, "qcom,pipe-early-release");
 		i++;
 	}
 
@@ -560,7 +581,8 @@ bool sde_splash_query_plane_is_reserved(struct sde_splash_info *sinfo,
 		return false;
 
 	for (i = 0; i < MAX_BLOCKS; i++) {
-		if (sinfo->reserved_pipe_info[i] == pipe)
+		if (!sinfo->reserved_pipe_info[i].early_release &&
+			(sinfo->reserved_pipe_info[i].pipe_id == pipe))
 			return true;
 	}
 
@@ -948,6 +970,9 @@ int sde_splash_lk_stop_splash(struct msm_kms *kms,
 	mutex_lock(&sde_splash_lock);
 	if (_sde_splash_validate_commit(sde_kms, state) &&
 			sinfo->display_splash_enabled) {
+		/* release splash RGB layer */
+		_sde_splash_release_early_splash_layer(sinfo);
+
 		if (_sde_splash_lk_check()) {
 			_sde_splash_notify_lk_stop_splash();
 			error = _sde_splash_clear_mixer_blendstage(kms, state);
diff --git a/drivers/gpu/drm/msm/sde/sde_splash.h b/drivers/gpu/drm/msm/sde/sde_splash.h
index 8332c99c6f1b..1b333932c5db 100644
--- a/drivers/gpu/drm/msm/sde/sde_splash.h
+++ b/drivers/gpu/drm/msm/sde/sde_splash.h
@@ -35,7 +35,7 @@ struct splash_ctl_top {
 	struct splash_lm_hw lm[LM_MAX - LM_0];
 };
 
-struct sde_res_data {
+struct splash_res_data {
 	struct splash_ctl_top top[CTL_MAX - CTL_0];
 	u8 ctl_ids[CTL_MAX - CTL_0];
 	u8 lm_ids[LM_MAX - LM_0];
@@ -43,12 +43,17 @@ struct sde_res_data {
 	u8 lm_cnt;
 };
 
+struct splash_reserved_pipe_info {
+	uint32_t pipe_id;
+	bool early_release;
+};
+
 struct sde_splash_info {
 	/* handoff flag */
 	bool handoff;
 
 	/* current hw configuration */
-	struct sde_res_data res;
+	struct splash_res_data res;
 
 	/* flag of display splash status */
 	bool display_splash_enabled;
@@ -86,8 +91,8 @@ struct sde_splash_info {
 	/* registered dst connector count */
 	uint32_t dsi_connector_cnt;
 
-	/* reserved pipe info for early RVC */
-	uint32_t reserved_pipe_info[MAX_BLOCKS];
+	/* reserved pipe info both for early RVC and early splash */
+	struct splash_reserved_pipe_info reserved_pipe_info[MAX_BLOCKS];
 };
 
 /* APIs for early splash handoff functions */