diff options
| author | Abhinav Kumar <abhinavk@codeaurora.org> | 2018-09-14 19:11:57 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2018-09-28 15:40:16 -0700 |
| commit | 9c0b6d6409e46abb0f31453ff2e8b19bdcb3a1a6 (patch) | |
| tree | 33cbac69f61ab6cb939450f1fde3c066ef70e459 /drivers/gpu | |
| parent | 070bf44aba13d672db9295f2ef2e98204c8e70ff (diff) | |
drm/msm: fix HDR programming sequence for mastering infoframe
Fix the HDR programming sequence in the HDMI driver to make it
compatible as per the latest hardware programming guide.
Change-Id: Ife5d0ce675a9653e0e44a413bda68b98d506a205
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c | 30 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.h | 2 |
2 files changed, 24 insertions, 8 deletions
diff --git a/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c b/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c index 83141aaa48d3..716c91563cc1 100644 --- a/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c +++ b/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c @@ -2025,6 +2025,16 @@ struct drm_msm_ext_panel_hdr_metadata *hdr_meta) return; } + /* Setup the line number to send the packet on */ + packet_control = hdmi_read(hdmi, HDMI_GEN_PKT_CTRL); + packet_control |= BIT(16); + hdmi_write(hdmi, HDMI_GEN_PKT_CTRL, packet_control); + + /* Setup the packet to be sent every frame */ + packet_control = hdmi_read(hdmi, HDMI_GEN_PKT_CTRL); + packet_control |= BIT(1); + hdmi_write(hdmi, HDMI_GEN_PKT_CTRL, packet_control); + /* Setup Packet header and payload */ packet_header = type_code | (version << 8) | (length << 16); hdmi_write(hdmi, HDMI_GENERIC0_HDR, packet_header); @@ -2083,14 +2093,20 @@ struct drm_msm_ext_panel_hdr_metadata *hdr_meta) hdmi_write(hdmi, HDMI_GENERIC0_6, packet_payload); enable_packet_control: - /* - * GENERIC0_LINE | GENERIC0_CONT | GENERIC0_SEND - * Setup HDMI TX generic packet control - * Enable this packet to transmit every frame - * Enable HDMI TX engine to transmit Generic packet 1 - */ + + /* Flush the contents to the register */ + packet_control = hdmi_read(hdmi, HDMI_GEN_PKT_CTRL); + packet_control |= BIT(2); + hdmi_write(hdmi, HDMI_GEN_PKT_CTRL, packet_control); + + /* Clear the flush bit of the register */ + packet_control = hdmi_read(hdmi, HDMI_GEN_PKT_CTRL); + packet_control &= ~BIT(2); + hdmi_write(hdmi, HDMI_GEN_PKT_CTRL, packet_control); + + /* Start sending the packets*/ packet_control = hdmi_read(hdmi, HDMI_GEN_PKT_CTRL); - packet_control |= BIT(0) | BIT(1) | BIT(2) | BIT(16); + packet_control |= BIT(0); hdmi_write(hdmi, HDMI_GEN_PKT_CTRL, packet_control); } diff --git a/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.h b/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.h index 2aa8d9496c5b..9a15f40bb32c 100644 --- a/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.h +++ b/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.h @@ -224,7 +224,7 @@ enum hdmi_tx_scdc_access_type { #define HDMI_YUV420_24BPP_PCLK_TMDS_CH_RATE_RATIO 2 #define HDMI_RGB_24BPP_PCLK_TMDS_CH_RATE_RATIO 1 -#define HDMI_GEN_PKT_CTRL_CLR_MASK 0x7 +#define HDMI_GEN_PKT_CTRL_CLR_MASK 0x3f0007 /* for AVI program */ #define HDMI_AVI_INFOFRAME_BUFFER_SIZE \ |