diff options
| author | Dhaval Patel <pdhaval@codeaurora.org> | 2017-05-03 19:48:53 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2018-03-01 18:30:06 -0800 |
| commit | 99ebd8e9b8cf3a2663d677e505b968714bfbfb5a (patch) | |
| tree | 2264105beadd4f6d55fb187f16f6b0e687a4e975 /drivers/gpu | |
| parent | 07ec991ea1a1f719aca6d5c4f11c8df4bf02d5c9 (diff) | |
drm/msm/sde: fix flush configuration for physical encoder
The sde encoder merges the flush for both controller but
does not configure the split_flush_enable on mdp_top.
This causes stage-1 fault or vsync_failure because right
side lm/sspp are not getting updated on each update. This
patch enables the split_flush only for pingpong split case
and also checks the vsync status on correct register.
Change-Id: I66b3326f342d63dad0b8d78bd12e882accc1dfa9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c index d58c06de1684..2f89c571fcfc 100644 --- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c @@ -333,10 +333,24 @@ static void sde_encoder_phys_vid_underrun_irq(void *arg, int irq_idx) phys_enc); } +static bool _sde_encoder_phys_is_ppsplit(struct sde_encoder_phys *phys_enc) +{ + enum sde_rm_topology_name topology; + + if (!phys_enc) + return false; + + topology = sde_connector_get_topology_name(phys_enc->connector); + if (topology == SDE_RM_TOPOLOGY_PPSPLIT) + return true; + + return false; +} + static bool sde_encoder_phys_vid_needs_single_flush( struct sde_encoder_phys *phys_enc) { - return phys_enc && phys_enc->split_role != ENC_ROLE_SOLO; + return phys_enc && _sde_encoder_phys_is_ppsplit(phys_enc); } static int sde_encoder_phys_vid_register_irq(struct sde_encoder_phys *phys_enc, @@ -674,7 +688,7 @@ static int sde_encoder_phys_vid_wait_for_vblank( KICKOFF_TIMEOUT_MS); if (ret <= 0) { irq_status = sde_core_irq_read(phys_enc->sde_kms, - INTR_IDX_VSYNC, true); + vid_enc->irq_idx[INTR_IDX_VSYNC], true); if (irq_status) { SDE_EVT32(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0); |