diff options
| author | Jordan Crouse <jcrouse@codeaurora.org> | 2017-07-24 10:49:53 -0600 |
|---|---|---|
| committer | Jordan Crouse <jcrouse@codeaurora.org> | 2017-07-24 13:01:12 -0600 |
| commit | 8eac9a50f0e198a83667ddb7daf98d917accbab6 (patch) | |
| tree | ee1ccecbf65c71f94ba9b793cabc54803811b16c /drivers/gpu | |
| parent | cffa5f76da7cc59e61f50ae70d122158e318be2f (diff) | |
drm/msm: Check value of active_cnt in a5xx power functions
The generic msm_gpu_pm_resume/msm_gpu_pm_suspend functions have
built-in reference counting but the a5xx specific functions
are doing unconditional a5xx specific setup / teardown that
would behave very badly if they were not accompanied by an
actual power up / power down.
Change-Id: Ic0dedbad549c4ea9a5c68b0ca43eb98e0449d54b
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 35 |
1 files changed, 22 insertions, 13 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 37323e962c2c..386050a228a8 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1168,6 +1168,10 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) if (ret) return ret; + /* If we are already up, don't mess with what works */ + if (gpu->active_cnt > 1) + return 0; + /* Turn the RBCCU domain first to limit the chances of voltage droop */ gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000); @@ -1198,22 +1202,27 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - /* Clear the VBIF pipe before shutting down */ + /* Only do this next bit if we are about to go down */ + if (gpu->active_cnt == 1) { + /* Clear the VBIF pipe before shutting down */ - gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0xF); - spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & 0xF) == 0xF); + gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0xF); + spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & 0xF) + == 0xF); - gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0); - - /* - * Reset the VBIF before power collapse to avoid issue with FIFO - * entries - */ + gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0); - if (adreno_is_a530(adreno_gpu)) { - /* These only need to be done for A530 */ - gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000); - gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000); + /* + * Reset the VBIF before power collapse to avoid issue with FIFO + * entries + */ + if (adreno_is_a530(adreno_gpu)) { + /* These only need to be done for A530 */ + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, + 0x003C0000); + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, + 0x00000000); + } } return msm_gpu_pm_suspend(gpu); |