diff options
| author | Sushmita Susheelendra <ssusheel@codeaurora.org> | 2017-05-12 08:12:21 -0600 |
|---|---|---|
| committer | Sushmita Susheelendra <ssusheel@codeaurora.org> | 2017-05-31 12:00:54 -0600 |
| commit | 855e0a4c1c6b5257c2407c6f1f6210d2be5534f2 (patch) | |
| tree | 70ce4b29d642d6509204bab758c1873af3e902bb /drivers/gpu | |
| parent | b39c609072d556dc39117e162cd396f7f4aea660 (diff) | |
drm/msm: Set the TTBR1 range for a 36-bit address space
Define a 36-bit address space for TTBR1 which is used for
kernel side GPU buffer objects.
Change-Id: I1c4eaee0fd92236793621c7d3dba1700e56fefd2
Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 3caa460aa5ba..f70e67766d19 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1408,8 +1408,8 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) * Set the user domain range to fall into the TTBR1 region for global * objects */ - a5xx_config.va_start = 0x800000000; - a5xx_config.va_end = 0x8ffffffff; + a5xx_config.va_start = 0xfffffff000000000ULL; + a5xx_config.va_end = 0xffffffffffffffffULL; a5xx_config.secure_va_start = SECURE_VA_START; a5xx_config.secure_va_end = SECURE_VA_START + SECURE_VA_SIZE - 1; |