drm/msm: Set IOMMU flags in the IOMMU specific code

Pass the bo flags all the way down to the iommu map code and
translate into the IOMMU flags right before mapping. This crosses the
streams a bit by moving BO level knowledge all the way down into the
MMU driver but it removes IOMMU specific knowledge from the address
space level which will be important when the address space code for
the GPU and the display are merged into one.

Change-Id: Ic0dedbad256f8986658bbe50fc2e2bd4051b7a7c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

4 files changed, 16 insertions, 15 deletions

diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c
index a227f1ba0573..2a4906752b70 100644
--- a/drivers/gpu/drm/msm/msm_gem_vma.c
+++ b/drivers/gpu/drm/msm/msm_gem_vma.c
@@ -141,16 +141,6 @@ static int iommu_aspace_map_vma(struct msm_gem_address_space *aspace,
 	size_t size = 0;
 	struct scatterlist *sg;
 	int ret, i;
-	int iommu_flags = IOMMU_READ;
-
-	if (!(flags & MSM_BO_GPU_READONLY))
-		iommu_flags |= IOMMU_WRITE;
-
-	if (flags & MSM_BO_PRIVILEGED)
-		iommu_flags |= IOMMU_PRIV;
-
-	if ((flags & MSM_BO_CACHED) && msm_iommu_coherent(aspace->mmu))
-		iommu_flags |= IOMMU_CACHE;
 
 	if (WARN_ON(drm_mm_node_allocated(&vma->node)))
 		return 0;
@@ -167,7 +157,7 @@ static int iommu_aspace_map_vma(struct msm_gem_address_space *aspace,
 
 	if (aspace->mmu)
 		ret = aspace->mmu->funcs->map(aspace->mmu, vma->iova, sgt,
-			iommu_flags);
+			flags);
 
 	/* Get a reference to the aspace to keep it around */
 	kref_get(&aspace->kref);
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index 3af24646f4f1..99579bfaadef 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -196,7 +196,7 @@ static void msm_iommu_detach_dynamic(struct msm_mmu *mmu)
 }
 
 static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
-		struct sg_table *sgt, int prot)
+		struct sg_table *sgt, u32 flags)
 {
 	struct msm_iommu *iommu = to_msm_iommu(mmu);
 	struct iommu_domain *domain = iommu->domain;
@@ -204,10 +204,20 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
 	uint64_t da = iova;
 	unsigned int i, j;
 	int ret;
+	u32 prot = IOMMU_READ;
 
 	if (!domain || !sgt)
 		return -EINVAL;
 
+	if (!(flags & MSM_BO_GPU_READONLY))
+		prot |= IOMMU_WRITE;
+
+	if (flags & MSM_BO_PRIVILEGED)
+		prot |= IOMMU_PRIV;
+
+	if ((flags & MSM_BO_CACHED) && msm_iommu_coherent(mmu))
+		prot |= IOMMU_CACHE;
+
 	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
 		phys_addr_t pa = sg_phys(sg) - sg->offset;
 		size_t bytes = sg->length + sg->offset;
diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h
index 501f12bef00d..4d8f55c1d7d5 100644
--- a/drivers/gpu/drm/msm/msm_mmu.h
+++ b/drivers/gpu/drm/msm/msm_mmu.h
@@ -34,7 +34,7 @@ struct msm_mmu_funcs {
 	int (*attach)(struct msm_mmu *mmu, const char **names, int cnt);
 	void (*detach)(struct msm_mmu *mmu);
 	int (*map)(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt,
-			int prot);
+			u32 flags);
 	int (*unmap)(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt);
 	int (*map_sg)(struct msm_mmu *mmu, struct sg_table *sgt,
 			enum dma_data_direction dir);
diff --git a/drivers/gpu/drm/msm/msm_smmu.c b/drivers/gpu/drm/msm/msm_smmu.c
index c99f51e09700..5cdcde12ee52 100644
--- a/drivers/gpu/drm/msm/msm_smmu.c
+++ b/drivers/gpu/drm/msm/msm_smmu.c
@@ -105,7 +105,7 @@ static void msm_smmu_detach(struct msm_mmu *mmu)
 }
 
 static int msm_smmu_map(struct msm_mmu *mmu, uint64_t iova,
-		struct sg_table *sgt, int prot)
+		struct sg_table *sgt, u32 flags)
 {
 	struct msm_smmu *smmu = to_msm_smmu(mmu);
 	struct msm_smmu_client *client = msm_smmu_to_client(smmu);
@@ -128,7 +128,8 @@ static int msm_smmu_map(struct msm_mmu *mmu, uint64_t iova,
 
 		VERB("map[%d]: %16llx %08x(%zx)", i, iova, pa, bytes);
 
-		ret = iommu_map(domain, da, pa, bytes, prot);
+		ret = iommu_map(domain, da, pa, bytes,
+			IOMMU_READ | IOMMU_WRITE);
 		if (ret)
 			goto fail;