diff options
| author | Venkateswara Rao Tadikonda <vtadik@codeaurora.org> | 2018-01-25 14:38:29 +0530 |
|---|---|---|
| committer | Venkateswara Rao Tadikonda <vtadik@codeaurora.org> | 2018-02-05 15:51:15 +0530 |
| commit | 0a281e5e64c09dea99e3f2068ae223a2beb7d40a (patch) | |
| tree | 9f59de7fb15a00547170fe8f47b8cba16e47e759 /drivers/gpu | |
| parent | e8df2440a48f8459083f1d7625d2e125e2b34881 (diff) | |
drm/msm: Corrected CCU load bit configuration
CCU load_bit is supposed to be configured for RB_PERFCTR_CCU register, but
it is configured for RB_POWERCTR_CCU register. Updated the RB_PERFCTR_CCU
register configuration with CCU load_bit.
Change-Id: I3b4ce056923b5bd39bc274a0744008f5bc5db0f1
Signed-off-by: Venkateswara Rao Tadikonda <vtadik@codeaurora.org>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a5xx_counters.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_counters.c b/drivers/gpu/drm/msm/adreno/a5xx_counters.c index 1d5e61daca47..a1b88529b986 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_counters.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_counters.c @@ -355,13 +355,13 @@ static struct adreno_counter a5xx_counters_alwayson[1] = { static struct adreno_counter a5xx_counters_ccu[] = { { REG_A5XX_RBBM_PERFCTR_CCU_0_LO, REG_A5XX_RBBM_PERFCTR_CCU_0_HI, - REG_A5XX_RB_PERFCTR_CCU_SEL_0 }, + REG_A5XX_RB_PERFCTR_CCU_SEL_0, 40 }, { REG_A5XX_RBBM_PERFCTR_CCU_1_LO, REG_A5XX_RBBM_PERFCTR_CCU_1_HI, - REG_A5XX_RB_PERFCTR_CCU_SEL_1 }, + REG_A5XX_RB_PERFCTR_CCU_SEL_1, 41 }, { REG_A5XX_RBBM_PERFCTR_CCU_2_LO, REG_A5XX_RBBM_PERFCTR_CCU_2_HI, - REG_A5XX_RB_PERFCTR_CCU_SEL_2 }, + REG_A5XX_RB_PERFCTR_CCU_SEL_2, 42 }, { REG_A5XX_RBBM_PERFCTR_CCU_3_LO, REG_A5XX_RBBM_PERFCTR_CCU_3_HI, - REG_A5XX_RB_PERFCTR_CCU_SEL_3 }, + REG_A5XX_RB_PERFCTR_CCU_SEL_3, 43 }, }; static struct adreno_counter a5xx_counters_cmp[] = { @@ -599,9 +599,9 @@ static struct adreno_counter a5xx_counters_vsc[] = { static struct adreno_counter a5xx_counters_power_ccu[] = { { REG_A5XX_CCU_POWER_COUNTER_0_LO, REG_A5XX_CCU_POWER_COUNTER_0_HI, - REG_A5XX_RB_POWERCTR_CCU_SEL_0, 40 }, + REG_A5XX_RB_POWERCTR_CCU_SEL_0 }, { REG_A5XX_CCU_POWER_COUNTER_1_LO, REG_A5XX_CCU_POWER_COUNTER_1_HI, - REG_A5XX_RB_POWERCTR_CCU_SEL_1, 41 }, + REG_A5XX_RB_POWERCTR_CCU_SEL_1 }, }; static struct adreno_counter a5xx_counters_power_cp[] = { |