Merge tag 'LA.UM.8.4.r1-05900-8x98.0' of https://source.codeaurora.org/quic/la/kernel/msm-4.4 into lineage-17.1-caf-msm8998

* tag 'LA.UM.8.4.r1-05900-8x98.0' of https://source.codeaurora.org/quic/la/kernel/msm-4.4:
  msm: kgsl: Mark the scratch buffer as privileged
  power: qcom: Add the QPNP QGAUGE (QG) headers
  msm: ipa: update msm_ipa.h with latest IPA versions constants
  nl80211: add NL80211_CMD_UPDATE_FT_IES to supported commands
  msm: mdss: hdmi: proper error logging
  ASoC: Fix warnings and errors with llvm
  sdm660_cdc: Reset cache_only mode for non SSR scenario
  include: Fix for compilation issue
  Makefile: Suppress few warnings with clang
  kbuild: Add -Werror=unknown-warning-option to CLANG_FLAGS
  kbuild: initialize CLANG_FLAGS correctly in the top Makefile
  kbuild: consolidate Clang compiler flags
  kbuild: add -no-integrated-as Clang option unconditionally
  power: qpnp-fg-gen3: Fix warning with llvm
  lkdtm: Fix warning with llvm
  AndroidKernel: Explicitly mark certain targets as phony
  dsp: q6asm: Change to increase asm sessions allowed
  dsp: q6adm: Channel map configuration for multi-channel
  defconfig: Create symbolic link for arm64 defconfigs
  scripts/build-all: remove pattern-based defconfig detection
  scripts/build-all: look for nested vendor/ defconfig directories
  scripts/build-all: remove all defconfig manipulation options
  scripts: build-all.py: update regex to compile all defconfigs
  scripts: build-all.py: append llvm to the config file
  scripts: Clean up the gcc-wrapper white list
  scripts: set clang as REAL_CC to support LLVM by default
  defconfig: auto: remove auto defconfigs
  vgacon: Fix a UAF in vgacon_invert_region
  soc: qcom: Reset string table index for each dump collection request
  msm: adsprpc: Fix array index underflow problem
  ath10k: remove unnecessary code
  drm/msm/dsi: use correct enum in dsi_get_cmd_fmt
  btrfs: Remove extra parentheses from condition in copy_items()
  do_last(): fetch directory ->i_mode and ->i_uid before it's too late

Conflicts:
	fs/namei.c
	scripts/gcc-wrapper.py

Change-Id: Icfb78abcc0f2cf980b5c0ceaf40f108038b1b527

1 files changed, 43 insertions, 3 deletions

diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 3a3777823013..ca0bd35e6348 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2002,2007-2017,2019, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2002,2007-2017,2019-2020, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -138,7 +138,7 @@ void adreno_ringbuffer_submit(struct adreno_ringbuffer *rb,
 	adreno_ringbuffer_wptr(adreno_dev, rb);
 }
 
-int adreno_ringbuffer_submit_spin(struct adreno_ringbuffer *rb,
+int adreno_ringbuffer_submit_spin_nosync(struct adreno_ringbuffer *rb,
 		struct adreno_submit_time *time, unsigned int timeout)
 {
 	struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);
@@ -147,6 +147,38 @@ int adreno_ringbuffer_submit_spin(struct adreno_ringbuffer *rb,
 	return adreno_spin_idle(adreno_dev, timeout);
 }
 
+/*
+ * adreno_ringbuffer_submit_spin() - Submit the cmds and wait until GPU is idle
+ * @rb: Pointer to ringbuffer
+ * @time: Pointer to adreno_submit_time
+ * @timeout: timeout value in ms
+ *
+ * Add commands to the ringbuffer and wait until GPU goes to idle. This routine
+ * inserts a WHERE_AM_I packet to trigger a shadow rptr update. So, use
+ * adreno_ringbuffer_submit_spin_nosync() if the previous cmd in the RB is a
+ * CSY packet because CSY followed by WHERE_AM_I is not legal..
+ */
+int adreno_ringbuffer_submit_spin(struct adreno_ringbuffer *rb,
+		struct adreno_submit_time *time, unsigned int timeout)
+{
+	struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);
+	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+	unsigned int *cmds;
+
+	if (adreno_is_a3xx(adreno_dev))
+		return adreno_ringbuffer_submit_spin_nosync(rb, time, timeout);
+
+	cmds = adreno_ringbuffer_allocspace(rb, 3);
+	if (IS_ERR(cmds))
+		return PTR_ERR(cmds);
+
+	*cmds++ = cp_packet(adreno_dev, CP_WHERE_AM_I, 2);
+	cmds += cp_gpuaddr(adreno_dev, cmds,
+			SCRATCH_RPTR_GPU_ADDR(device, rb->id));
+
+	return adreno_ringbuffer_submit_spin_nosync(rb, time, timeout);
+}
+
 unsigned int *adreno_ringbuffer_allocspace(struct adreno_ringbuffer *rb,
 		unsigned int dwords)
 {
@@ -273,11 +305,12 @@ int adreno_ringbuffer_probe(struct adreno_device *adreno_dev, bool nopreempt)
 {
 	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
+	unsigned int priv = KGSL_MEMDESC_RANDOM | KGSL_MEMDESC_PRIVILEGED;
 	int i, status;
 
 	if (!adreno_is_a3xx(adreno_dev)) {
 		status = kgsl_allocate_global(device, &device->scratch,
-				PAGE_SIZE, 0, KGSL_MEMDESC_RANDOM, "scratch");
+				PAGE_SIZE, 0, priv, "scratch");
 		if (status != 0)
 			return status;
 	}
@@ -480,6 +513,8 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
 	if (gpudev->preemption_post_ibsubmit &&
 				adreno_is_preemption_enabled(adreno_dev))
 		total_sizedwords += 5;
+	else if (!adreno_is_a3xx(adreno_dev))
+		total_sizedwords += 3;
 
 	/*
 	 * a5xx uses 64 bit memory address. pm4 commands that involve read/write
@@ -670,6 +705,11 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
 				adreno_is_preemption_enabled(adreno_dev))
 		ringcmds += gpudev->preemption_post_ibsubmit(adreno_dev,
 			ringcmds);
+	else if (!adreno_is_a3xx(adreno_dev)) {
+		*ringcmds++ = cp_packet(adreno_dev, CP_WHERE_AM_I, 2);
+		ringcmds += cp_gpuaddr(adreno_dev, ringcmds,
+				SCRATCH_RPTR_GPU_ADDR(device, rb->id));
+	}
 
 	/*
 	 * If we have more ringbuffer commands than space reserved