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| author | Gaurav K Singh <gaurav.k.singh@intel.com> | 2015-07-01 15:58:52 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-07-03 07:39:02 +0200 |
| commit | 20dbe1a1cbf3f1f0a6a07581e5b95ae027c9bea0 (patch) | |
| tree | c7a72f4556b48dc2e72f037e4587e0ed3abd7a59 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | 3c5c6d88855baf9c3b9aa6243a37bb179f5a737e (diff) | |
drm/i915: Changes required to enable DSI Video Mode on CHT
On CHT, changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct
dividor & ctrl values are written in cck regs for DSI. This patch has
been tested on CHT RVP with 1200 x 1920 panel.
v2 by Jani, rebased on earlier refactoring, original at [1].
[1] http://mid.gmane.org/1431368400-1942-5-git-send-email-rodrigo.vivi@intel.com
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions