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| author | Linux Build Service Account <lnxbuild@localhost> | 2016-10-26 13:13:25 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-10-26 13:13:24 -0700 |
| commit | bcd8ec9210c9048c14d934e16267ba79a894db09 (patch) | |
| tree | 7e3f49424f21431eab08f679ea6213d6dfa32d1c /drivers/gpu/drm/i915/intel_pm.c | |
| parent | b12304a53614f77f37dd87b470ae76084e768966 (diff) | |
| parent | 617229a3e9400c58b578077ff6f81d2f25a1f5ff (diff) | |
Merge "Merge remote-tracking branch 'msm-4.4/tmp-510d0a3f' into msm-4.4"
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f091ad12d694..0a68d2ec89dc 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6620,6 +6620,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev) misccpctl = I915_READ(GEN7_MISCCPCTL); I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); + /* + * Wait at least 100 clocks before re-enabling clock gating. See + * the definition of L3SQCREG1 in BSpec. + */ + POSTING_READ(GEN8_L3SQCREG1); + udelay(1); I915_WRITE(GEN7_MISCCPCTL, misccpctl); /* |