diff options
| author | Sivanesan Rajapupathi <srajap@codeaurora.org> | 2016-02-26 09:55:07 -0500 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-25 16:03:47 -0700 |
| commit | a60452973a5a24537fb714bb368a4c5607dd581f (patch) | |
| tree | 76a3812b4c78c4eba4fc2bcfa9fde0dab8db50d8 /drivers/crypto | |
| parent | d8ac7720f0b8f81d4343e19ad555a96956acc31b (diff) | |
crypto: msm: qce50: enable BAM SPS_BAM_CACHED_WP
Enable SPS_BAM_CACHED_WP option. The BAM register access is very slow.
The write descriptor offset information in the BAM_P_EVENT_REG is only
set by the host if BAM is runnig in system mode, such as NDP-BAM of crypto.
On each BAM transfter, driver reads the register to figure if
there is enough space to put in new descriptor. Reading the register can be
from driver cache copy, instead of going out to read the register if
SPS_BAM_CACHED_WP option is enabled.
Change-Id: I4c25f81ea79c9a8675d92b799844d906a42bcbb0
Acked-by: Che-Min Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Sivanesan Rajapupathi <srajap@codeaurora.org>
Diffstat (limited to 'drivers/crypto')
| -rw-r--r-- | drivers/crypto/msm/qce50.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/crypto/msm/qce50.c b/drivers/crypto/msm/qce50.c index 60b8e6de166e..6bcc08e94657 100644 --- a/drivers/crypto/msm/qce50.c +++ b/drivers/crypto/msm/qce50.c @@ -2871,6 +2871,7 @@ static int qce_sps_get_bam(struct qce_device *pce_dev) bam.ee = pce_dev->ce_bam_info.bam_ee; bam.ipc_loglevel = QCE_BAM_DEFAULT_IPC_LOGLVL; + bam.options |= SPS_BAM_CACHED_WP; pr_debug("bam physical base=0x%lx\n", (uintptr_t)bam.phys_addr); pr_debug("bam virtual base=0x%p\n", bam.virt_addr); |