clk: qcom: mdss: add support for dynamic refresh on DSI 14nm PLL

Add CLK_SET_RATE_NO_REPARENT flag for the software mux clocks in
DSI 14nm PLL driver which is needed for dynamic refresh feature.
Update the dynamic fps structure to align the PLL codes with
vco frequency instead of fps.

Change-Id: I533f615ce51be7229171b6accac3f14ab2dca949
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>

3 files changed, 22 insertions, 20 deletions

diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-14nm-util.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-14nm-util.c
index d388073f5f42..b885428d3eb7 100644
--- a/drivers/clk/qcom/mdss/mdss-dsi-pll-14nm-util.c
+++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-14nm-util.c
@@ -41,13 +41,13 @@ static int mdss_pll_read_stored_trim_codes(
 		goto end_read;
 	}
 
-	for (i = 0; i < dsi_pll_res->dfps->panel_dfps.frame_rate_cnt; i++) {
+	for (i = 0; i < dsi_pll_res->dfps->vco_rate_cnt; i++) {
 		struct dfps_codes_info *codes_info =
 			&dsi_pll_res->dfps->codes_dfps[i];
 
-		pr_debug("valid=%d frame_rate=%d, vco_rate=%d, code %d %d\n",
-			codes_info->is_valid, codes_info->frame_rate,
-			codes_info->clk_rate, codes_info->pll_codes.pll_codes_1,
+		pr_debug("valid=%d vco_rate=%d, code %d %d\n",
+			codes_info->is_valid, codes_info->clk_rate,
+			codes_info->pll_codes.pll_codes_1,
 			codes_info->pll_codes.pll_codes_2);
 
 		if (vco_clk_rate != codes_info->clk_rate &&
@@ -953,7 +953,13 @@ static void shadow_pll_dynamic_refresh_14nm(struct mdss_pll_resources *pll,
 							struct dsi_pll_db *pdb)
 {
 	struct dsi_pll_output *pout = &pdb->out;
+	u32 data = 0;
 
+	data = (pout->pll_n1div | (pout->pll_n2div << 4));
+	MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
+		DSI_DYNAMIC_REFRESH_PLL_CTRL19,
+		DSIPHY_CMN_CLK_CFG0, DSIPHY_CMN_CLK_CFG1,
+		data, 1);
 	MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
 		DSI_DYNAMIC_REFRESH_PLL_CTRL20,
 		DSIPHY_CMN_CTRL_0, DSIPHY_PLL_SYSCLK_EN_RESET,
diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-14nm.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-14nm.c
index 667a1512d54f..bf3532133487 100644
--- a/drivers/clk/qcom/mdss/mdss-dsi-pll-14nm.c
+++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-14nm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2016, 2018 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -323,7 +323,8 @@ static struct clk_regmap_mux dsi0pll_pixel_clk_mux = {
 				(const char *[]){ "dsi0pll_pixel_clk_src",
 					"dsi0pll_shadow_pixel_clk_src"},
 			.num_parents = 2,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |
+				CLK_SET_RATE_NO_REPARENT),
 			.ops = &clk_regmap_mux_closest_ops,
 		},
 	},
@@ -341,7 +342,8 @@ static struct clk_regmap_mux dsi1pll_pixel_clk_mux = {
 				(const char *[]){ "dsi1pll_pixel_clk_src",
 					"dsi1pll_shadow_pixel_clk_src"},
 			.num_parents = 2,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |
+				CLK_SET_RATE_NO_REPARENT),
 			.ops = &clk_regmap_mux_closest_ops,
 		},
 	},
@@ -414,7 +416,8 @@ static struct clk_regmap_mux dsi0pll_byte_clk_mux = {
 					"dsi0pll_shadow_byte_clk_src"},
 			.num_parents = 2,
 			.ops = &clk_regmap_mux_closest_ops,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |
+				CLK_SET_RATE_NO_REPARENT),
 		},
 	},
 };
@@ -432,7 +435,8 @@ static struct clk_regmap_mux dsi1pll_byte_clk_mux = {
 					"dsi1pll_shadow_byte_clk_src"},
 			.num_parents = 2,
 			.ops = &clk_regmap_mux_closest_ops,
-			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
+			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |
+				CLK_SET_RATE_NO_REPARENT),
 		},
 	},
 };
diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h
index 369c36407ff7..5af107db8b1b 100644
--- a/drivers/clk/qcom/mdss/mdss-pll.h
+++ b/drivers/clk/qcom/mdss/mdss-pll.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -57,13 +57,7 @@ enum {
 	MDSS_PLL_TARGET_SDM630,
 };
 
-#define DFPS_MAX_NUM_OF_FRAME_RATES 20
-
-struct dfps_panel_info {
-	uint32_t enabled;
-	uint32_t frame_rate_cnt;
-	uint32_t frame_rate[DFPS_MAX_NUM_OF_FRAME_RATES]; /* hz */
-};
+#define DFPS_MAX_NUM_OF_FRAME_RATES 16
 
 struct dfps_pll_codes {
 	uint32_t pll_codes_1;
@@ -72,15 +66,13 @@ struct dfps_pll_codes {
 
 struct dfps_codes_info {
 	uint32_t is_valid;
-	uint32_t frame_rate;	/* hz */
 	uint32_t clk_rate;	/* hz */
 	struct dfps_pll_codes pll_codes;
 };
 
 struct dfps_info {
-	struct dfps_panel_info panel_dfps;
+	uint32_t vco_rate_cnt;
 	struct dfps_codes_info codes_dfps[DFPS_MAX_NUM_OF_FRAME_RATES];
-	void *dfps_fb_base;
 };
 
 struct mdss_pll_resources {