diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-02-22 11:35:26 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:21:21 -0700 |
| commit | 665fc9f340c4381353a7669ca70416e738d95f97 (patch) | |
| tree | acd9e505cea3011b593599ef41501174195302af /drivers/clk | |
| parent | d00e0ab13b8e900fb620244e3ec0e604b27f97eb (diff) | |
clk: msm: clock: Program delay time for droop detector recalibration
Configure the RECAL_VCTL/CPR_DLY registers to enable and set the
voltage delay time for hardware based droop detector recalibration.
Only needed on MSM8996 Pro.
CRs-Fixed: 980641
Change-Id: I217e4510b020b7708665394c42f46773bd8b225d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/msm/clock-cpu-8996.c | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/drivers/clk/msm/clock-cpu-8996.c b/drivers/clk/msm/clock-cpu-8996.c index 8038fed7bcbe..8efef472a2fc 100644 --- a/drivers/clk/msm/clock-cpu-8996.c +++ b/drivers/clk/msm/clock-cpu-8996.c @@ -1457,6 +1457,7 @@ module_exit(cpu_clock_8996_exit); #define CBF_BASE_PHY 0x09A11000 #define CBF_PLL_BASE_PHY 0x09A20000 #define AUX_BASE_PHY 0x09820050 +#define APCC_RECAL_DLY_BASE 0x099E00C8 #define CLK_CTL_OFFSET 0x44 #define PSCTL_OFFSET 0x164 @@ -1464,6 +1465,10 @@ module_exit(cpu_clock_8996_exit); #define CBF_AUTO_CLK_SEL_BIT BIT(6) #define AUTO_CLK_SEL_ALWAYS_ON_MASK BM(5, 4) #define AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL (0x3 << 4) +#define APCC_RECAL_DLY_SIZE 0x10 +#define APCC_RECAL_VCTL_OFFSET 0x8 +#define APCC_RECAL_CPR_DLY_SETTING 0x00000000 +#define APCC_RECAL_VCTL_DLY_SETTING 0x800003ff #define HF_MUX_MASK 0x3 #define LF_MUX_MASK 0x3 @@ -1502,7 +1507,7 @@ static struct notifier_block __refdata clock_cpu_8996_cpu_notifier = { int __init cpu_clock_8996_early_init(void) { int ret = 0; - void __iomem *auxbase; + void __iomem *auxbase, *acd_recal_base; u32 regval; if (of_find_compatible_node(NULL, NULL, @@ -1577,6 +1582,13 @@ int __init cpu_clock_8996_early_init(void) goto auxbase_fail; } + acd_recal_base = ioremap(APCC_RECAL_DLY_BASE, APCC_RECAL_DLY_SIZE); + if (!acd_recal_base) { + WARN(1, "Unable to ioremap ACD recal base. Can't configure ACD\n"); + ret = -ENOMEM; + goto acd_recal_base_fail; + } + /* * Set GPLL0 divider for div-2 to get 300Mhz. This divider * can be programmed dynamically. @@ -1768,6 +1780,21 @@ int __init cpu_clock_8996_early_init(void) writel_relaxed(0x3, vbases[APC1_BASE] + MDD_DROOP_CODE); /* + * Ensure that the writes go through before going + * forward. + */ + wmb(); + + /* + * Program the DLY registers to set a voltage settling + * delay time for HW based ACD recalibration. + */ + writel_relaxed(APCC_RECAL_CPR_DLY_SETTING, + acd_recal_base); + writel_relaxed(APCC_RECAL_VCTL_DLY_SETTING, + acd_recal_base + + APCC_RECAL_VCTL_OFFSET); + /* * Ensure that the writes go through before enabling * ACD. */ @@ -1812,6 +1839,8 @@ int __init cpu_clock_8996_early_init(void) */ pr_info("%s: finished CPU clock configuration\n", __func__); + iounmap(acd_recal_base); +acd_recal_base_fail: iounmap(auxbase); auxbase_fail: iounmap(vbases[CBF_PLL_BASE]); |