diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2016-11-14 21:53:58 -0800 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-11-14 21:53:57 -0800 |
| commit | 1f3e1e09867c04f330894f7358a3dbbd2aaa0b78 (patch) | |
| tree | 85546d90cbc4a17776301f21ee795a84eac6cc80 /drivers/clk | |
| parent | cda3134eb149e1562b9ca828357335a748792230 (diff) | |
| parent | fa8b3ea588393dd1e40fdd29c4bd3cd1c33fbc55 (diff) | |
Merge "clk: msm: mdss: fix divider configuration for 5.4 Ghz link rate"
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c b/drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c index f23f32f7e37a..93bbcf5d40f5 100644 --- a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c +++ b/drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c @@ -275,7 +275,7 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate) MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00); MDSS_PLL_REG_W(dp_res->pll_base, - QSERDES_COM_DIV_FRAC_START3_MODE0, 0xa0); + QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a); MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_CMN_CONFIG, 0x12); MDSS_PLL_REG_W(dp_res->pll_base, |