diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-08-23 14:03:05 -0700 |
|---|---|---|
| committer | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-09-07 09:59:04 -0700 |
| commit | d9b8af23aa380ab24ab90557149018cede3d7d30 (patch) | |
| tree | 5e1c0060a73aec2655b2a62e2fdd5d2112252b45 /arch | |
| parent | 26745af0124e3ff541e01cd32fca2bddb97784bf (diff) | |
clk: msm: clock: Vote on MX rail on behalf of MM PLLs on MSMCOBALT
The multimedia PLLs are all in the MX domain on MSMCOBALT. Replace
voting on the CX rail with voting for MX voltages from the clock
driver. In addition, update the MMPLL7 FMAX table.
CRs-Fixed: 1063153
Change-Id: I296d2b151753be599a1db139e36f5e1eabe76791
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 4ea1cf31c4dc..b7e866a2b9e4 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -745,6 +745,7 @@ reg = <0xc8c0000 0x40000>; reg-names = "cc_base"; vdd_dig-supply = <&pmcobalt_s1_level>; + vdd_mmsscc_mx-supply = <&pmcobalt_s9_level>; clock-names = "xo", "gpll0", "gpll0_div", "pclk0_src", "pclk1_src", "byte0_src", "byte1_src", |