diff options
| author | Viswanadha Raju Thotakura <viswanad@codeaurora.org> | 2016-07-27 14:52:58 -0700 |
|---|---|---|
| committer | Viswanadha Raju Thotakura <viswanad@codeaurora.org> | 2016-08-05 15:33:31 -0700 |
| commit | b43b062f24445ea0b154ed86deaa222bfc17a89e (patch) | |
| tree | b16f7f9001d4224562471670fab2ecaea44561c6 /arch | |
| parent | f600d8b9ec91f477d6b7a83cb60c83d15de51167 (diff) | |
ARM: dts: msm: Modify csiphy timer clock rate on msmcobalt
Set csiphy timer clock rate to SVS for normal data rate
operations.
CRs-Fixed: 1043041
Change-Id: Ia6fc2dcfa7b5fd23eb2af5baf0acb9fd161fdd09
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi index a3911ea7a89d..b11c68ae543e 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi @@ -48,7 +48,7 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0 + qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 0 256000000 0>; status = "ok"; }; @@ -80,7 +80,7 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0 + qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 0 256000000 0>; status = "ok"; }; @@ -112,7 +112,7 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0 + qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 0 256000000 0>; status = "ok"; }; |