diff options
| author | Osvaldo Banuelos <osvaldob@codeaurora.org> | 2016-02-29 13:35:37 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-25 16:04:01 -0700 |
| commit | b1d55b705b31628df6df0e926cc6cf7f33f2f371 (patch) | |
| tree | e8e394845aab997ff1beee5a17215bf8ee6e6850 /arch | |
| parent | e7262e36a5ddb72c9ecf14ea7b2f675e52a904d0 (diff) | |
ARM: dts: msm: Define OSM cycle counter parameters for msmcobalt
Define the OSM and XO clock rates necessary for performance
estimation using the OSM cycle counter. These parameters vary
based upon the platform.
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
CRs-Fixed: 987865
Change-Id: I721dc3488484b66e3f88cbebf626e88176f08a44
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-sim.dts | 6 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 4 |
2 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-sim.dts b/arch/arm/boot/dts/qcom/msmcobalt-sim.dts index b7d7f97a8250..0adfaefe69f2 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-sim.dts +++ b/arch/arm/boot/dts/qcom/msmcobalt-sim.dts @@ -27,6 +27,12 @@ status = "disabled"; }; +&clock_cpu { + qcom,cc-factor = <1>; + qcom,osm-clk-rate = <19200000>; + qcom,xo-clk-rate = <19200000>; +}; + &ufsphy1 { status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index cafd8a6e7cc2..2874cc0185ab 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -724,6 +724,10 @@ qcom,llm-volt-down-timer = <1 1>; qcom,cc-reads = <10>; + qcom,cc-delay = <5>; + qcom,cc-factor = <100>; + qcom,osm-clk-rate = <200000000>; + qcom,xo-clk-rate = <19200000>; qcom,l-val-base = <0x17916004 0x17816004>; |