diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-02-09 17:27:55 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:20:24 -0700 |
| commit | 96da03ab3132bc039d414c103d1e27e2e45f063e (patch) | |
| tree | 2af8bf7d3656727e64d15d87dc6bf3bce3a46be2 /arch | |
| parent | d5d3df187e6667b626a5e7ff4b1b146956834fde (diff) | |
clk: msm: clock-gpu-cobalt: Correct the CRC enable sequence
The GPU GDSCs need to be turned prior to enabling the graphics
clock and programming the CRC registers. Add that support.
CRs-Fixed: 974342
Change-Id: I4f97c10c383f79490c8dc428ef5ffb1040adc18d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 5a8351e40671..8fb875038c8a 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -410,9 +410,8 @@ clock_gpu: qcom,gpucc@5065000 { compatible = "qcom,gpucc-cobalt"; - reg = <0x5065000 0x9000>, - <0x50660a0 0x8>; - reg-names = "cc_base", "crc_sid_fsm"; + reg = <0x5065000 0x9000>; + reg-names = "cc_base"; vdd_gpucc-supply = <&pm8005_s1>; vdd_dig-supply = <&pmcobalt_s1_level>; vdd_mx-supply = <&pmcobalt_s9_level>; |