diff options
| author | Osvaldo Banuelos <osvaldob@codeaurora.org> | 2015-11-24 11:28:29 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:12:03 -0700 |
| commit | 6c8839e8b1835142f88fde3c2d18b323bbc4262e (patch) | |
| tree | b0eb182aa7cdb0a4fcc29f25b1888fdfacb465e0 /arch | |
| parent | 1e492a56bc4cff5a9476a57d475018b735942df1 (diff) | |
ARM: dts: msm: Program only L2 and L3 ACC SEL settings for msm8996
According to the latest hardware guidelines, only L2 and L3 cache
HMSS ACC settings need to be programmed based upon the level of
their voltage supplies. Update the apc0_pwrcl and apc1_perfcl mem_acc
regulator devices to adhere to this requirement.
Change-Id: I94032f6fbe5920a8d446c58c763afa29705e527a
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8996-regulator.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/qcom/msm8996-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8996-regulator.dtsi index 47ead774e30f..58892a5b1f1d 100644 --- a/arch/arm/boot/dts/qcom/msm8996-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-regulator.dtsi @@ -1310,7 +1310,7 @@ regulator-name = "apc0_pwrcl_mem_acc_corner"; regulator-min-microvolt = <1>; regulator-max-microvolt = <2>; - qcom,corner-acc-map = <0x3 0x0>; + qcom,corner-acc-map = <0x2 0x0>; qcom,acc-sel-l1-bit-pos = <0>; qcom,acc-sel-l1-bit-size = <2>; @@ -1323,7 +1323,7 @@ regulator-name = "apc1_perfcl_mem_acc_corner"; regulator-min-microvolt = <1>; regulator-max-microvolt = <2>; - qcom,corner-acc-map = <0x3 0x0>; + qcom,corner-acc-map = <0x2 0x0>; qcom,acc-sel-l1-bit-pos = <2>; qcom,acc-sel-l1-bit-size = <2>; |