diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2016-02-03 03:15:22 +0000 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@google.com> | 2018-02-05 08:58:34 -0800 |
| commit | 518b875ac8eb7080f3db4dd45d39fd08239f589f (patch) | |
| tree | 5956031e1a7b6ee2f540b5d59a54997080b8160b /arch | |
| parent | 9684a8cd1c07521cac2f57d7b834134ad864ac0d (diff) | |
UPSTREAM: MIPS: traps: Make sure secondary cores have a sane ebase register
We shouldn't trust that the secondary cores will have a sane ebase register
(either from the bootloader or during the hardware design phase) so use the
ebase address as calculated by the boot CPU.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Petri Gynther <pgynther@google.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12328/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit 04d83f948510f17f8f2ab320b2386f4b5fbd0bd4)
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/traps.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 2ad27a560f7f..e23f4775b10b 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2140,6 +2140,13 @@ void per_cpu_trap_init(bool is_boot_cpu) * o read IntCtl.IPFDC to determine the fast debug channel interrupt */ if (cpu_has_mips_r2_r6) { + /* + * We shouldn't trust a secondary core has a sane EBASE register + * so use the one calculated by the boot CPU. + */ + if (!is_boot_cpu) + write_c0_ebase(ebase); + cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; |