diff options
| author | Padmanabhan Komanduru <pkomandu@codeaurora.org> | 2017-06-23 16:50:05 +0530 |
|---|---|---|
| committer | Padmanabhan Komanduru <pkomandu@codeaurora.org> | 2017-10-10 18:23:25 +0530 |
| commit | 4f10d5d018cc9d72af7e64984a11bb5d6485ce67 (patch) | |
| tree | 91b2f31f15704e188ab9c6a3c39f5797e95b6e15 /arch | |
| parent | 54d865e4839fad4f725d35cf0646f0c44e65864d (diff) | |
ARM: dts: msm: add the dtsi entries for DP PLL clocks for msm8998
The parent of DP VCO divided mux clock needs to be set from the
Display Port driver based on the link rate. Add the dtsi entries
needs for this support for msm8998.
Change-Id: I76c2568579735f20106e40a359fd0052a2f51fbf
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-mdss.dtsi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/qcom/msm8998-mdss.dtsi b/arch/arm/boot/dts/qcom/msm8998-mdss.dtsi index 5708fce44378..fbde8d21f22c 100644 --- a/arch/arm/boot/dts/qcom/msm8998-mdss.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-mdss.dtsi @@ -497,12 +497,16 @@ <&clock_mmss clk_mmss_mdss_dp_link_clk>, <&clock_mmss clk_mmss_mdss_dp_link_intf_clk>, <&clock_mmss clk_mmss_mdss_dp_crypto_clk>, - <&clock_mmss clk_mmss_mdss_dp_pixel_clk>; + <&clock_mmss clk_mmss_mdss_dp_pixel_clk>, + <&mdss_dp_pll clk_vco_divided_clk_src_mux>, + <&mdss_dp_pll clk_vco_divsel_two_clk_src>, + <&mdss_dp_pll clk_vco_divsel_four_clk_src>; clock-names = "core_mnoc_clk", "core_iface_clk", "core_bus_clk", "core_mdp_core_clk", "core_alt_iface_clk", "core_aux_clk", "core_ref_clk_src", "core_ref_clk", "ctrl_link_clk", "ctrl_link_iface_clk", - "ctrl_crypto_clk", "ctrl_pixel_clk"; + "ctrl_crypto_clk", "ctrl_pixel_clk", "pixel_parent", + "pixel_clk_two_div", "pixel_clk_four_div"; qcom,dp-usbpd-detection = <&pmi8998_pdphy>; |