msm: camera: Add support for camera on version 2 of msmcobalt

EQ bias is enabled in of msmcobalt version 2 csiphy.
Differentiate this setting with new version 2 camera dt file.

CRs-Fixed: 1050172
Change-Id: I5781453f2b2a81b9cf5f7fb643e021b53879583e
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>

2 files changed, 112 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi
new file mode 100644
index 000000000000..99d80a3b3848
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+	qcom,csiphy@ca34000 {
+		cell-index = <0>;
+		compatible = "qcom,csiphy-v5.01", "qcom,csiphy";
+		reg = <0xca34000 0x1000>;
+		reg-names = "csiphy";
+		interrupts = <0 78 0>;
+		interrupt-names = "csiphy";
+		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
+			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
+			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
+			<&clock_mmss clk_mmss_camss_ahb_clk>,
+			<&clock_mmss clk_mmss_camss_top_ahb_clk>,
+			<&clock_mmss clk_csi0_clk_src>,
+			<&clock_mmss clk_mmss_camss_csi0_clk>,
+			<&clock_mmss clk_mmss_camss_cphy_csid0_clk>,
+			<&clock_mmss clk_csi0phytimer_clk_src>,
+			<&clock_mmss clk_mmss_camss_csi0phytimer_clk>,
+			<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
+			<&clock_mmss clk_csiphy_clk_src>,
+			<&clock_mmss clk_mmss_camss_csiphy0_clk>;
+		clock-names = "mnoc_maxi", "mnoc_ahb",
+			"bmic_smmu_ahb", "bmic_smmu_axi",
+			"camss_ahb_clk", "camss_top_ahb_clk",
+			"csi_src_clk", "csi_clk", "cphy_csid_clk",
+			"csiphy_timer_src_clk", "csiphy_timer_clk",
+			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
+		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
+			0 256000000 0>;
+		status = "ok";
+	};
+
+	qcom,csiphy@ca35000 {
+		cell-index = <1>;
+		compatible = "qcom,csiphy-v5.01", "qcom,csiphy";
+		reg = <0xca35000 0x1000>;
+		reg-names = "csiphy";
+		interrupts = <0 79 0>;
+		interrupt-names = "csiphy";
+		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
+			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
+			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
+			<&clock_mmss clk_mmss_camss_ahb_clk>,
+			<&clock_mmss clk_mmss_camss_top_ahb_clk>,
+			<&clock_mmss clk_csi1_clk_src>,
+			<&clock_mmss clk_mmss_camss_csi1_clk>,
+			<&clock_mmss clk_mmss_camss_cphy_csid1_clk>,
+			<&clock_mmss clk_csi1phytimer_clk_src>,
+			<&clock_mmss clk_mmss_camss_csi1phytimer_clk>,
+			<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
+			<&clock_mmss clk_csiphy_clk_src>,
+			<&clock_mmss clk_mmss_camss_csiphy1_clk>;
+		clock-names = "mnoc_maxi", "mnoc_ahb",
+			"bmic_smmu_ahb", "bmic_smmu_axi",
+			"camss_ahb_clk", "camss_top_ahb_clk",
+			"csi_src_clk", "csi_clk", "cphy_csid_clk",
+			"csiphy_timer_src_clk", "csiphy_timer_clk",
+			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
+		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
+			0 256000000 0>;
+		status = "ok";
+	};
+
+	qcom,csiphy@ca36000 {
+		cell-index = <2>;
+		compatible = "qcom,csiphy-v5.01", "qcom,csiphy";
+		reg = <0xca36000 0x1000>;
+		reg-names = "csiphy";
+		interrupts = <0 80 0>;
+		interrupt-names = "csiphy";
+		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
+			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
+			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
+			<&clock_mmss clk_mmss_camss_ahb_clk>,
+			<&clock_mmss clk_mmss_camss_top_ahb_clk>,
+			<&clock_mmss clk_csi2_clk_src>,
+			<&clock_mmss clk_mmss_camss_csi2_clk>,
+			<&clock_mmss clk_mmss_camss_cphy_csid2_clk>,
+			<&clock_mmss clk_csi2phytimer_clk_src>,
+			<&clock_mmss clk_mmss_camss_csi2phytimer_clk>,
+			<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
+			<&clock_mmss clk_csiphy_clk_src>,
+			<&clock_mmss clk_mmss_camss_csiphy2_clk>;
+		clock-names = "mnoc_maxi", "mnoc_ahb",
+			"bmic_smmu_ahb", "bmic_smmu_axi",
+			"camss_ahb_clk", "camss_top_ahb_clk",
+			"csi_src_clk", "csi_clk", "cphy_csid_clk",
+			"csiphy_timer_src_clk", "csiphy_timer_clk",
+			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
+		qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
+			0 256000000 0>;
+		status = "ok";
+	};
+};
+
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi
index 48a23b44b5b2..6cbb0df9f9f3 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi
@@ -17,6 +17,7 @@
  */
 
 #include "msmcobalt.dtsi"
+#include "msmcobalt-v2-camera.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. MSMCOBALT v2";