diff options
| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2014-08-06 23:36:12 -0700 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2014-08-06 23:36:12 -0700 |
| commit | 5e2aa2ed08e2e280121dc7cf5609c87d464f12ef (patch) | |
| tree | ca7d7b1480285e3b617fecc5b41f0ce150a82c32 /arch/mips/pmcs-msp71xx/msp_irq.c | |
| parent | f62d14a8072b9756db36ba394e2b267470a40240 (diff) | |
| parent | fc8104bc5a3f6f49d79f45f2706f79f77a9fb2ae (diff) | |
Merge branch 'next' into for-linus
Prepare first round of input updates for 3.17.
Diffstat (limited to 'arch/mips/pmcs-msp71xx/msp_irq.c')
| -rw-r--r-- | arch/mips/pmcs-msp71xx/msp_irq.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/arch/mips/pmcs-msp71xx/msp_irq.c b/arch/mips/pmcs-msp71xx/msp_irq.c index 9da5619c00a5..941744aabb51 100644 --- a/arch/mips/pmcs-msp71xx/msp_irq.c +++ b/arch/mips/pmcs-msp71xx/msp_irq.c @@ -32,7 +32,7 @@ extern void msp_vsmp_int_init(void); /* vectored interrupt implementation */ -/* SW0/1 interrupts are used for SMP/SMTC */ +/* SW0/1 interrupts are used for SMP */ static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); } static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); } static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); } @@ -138,14 +138,6 @@ void __init arch_init_irq(void) set_vi_handler(MSP_INT_SEC, sec_int_dispatch); #ifdef CONFIG_MIPS_MT_SMP msp_vsmp_int_init(); -#elif defined CONFIG_MIPS_MT_SMTC - /*Set hwmask for all platform devices */ - irq_hwmask[MSP_INT_MAC0] = C_IRQ0; - irq_hwmask[MSP_INT_MAC1] = C_IRQ1; - irq_hwmask[MSP_INT_USB] = C_IRQ2; - irq_hwmask[MSP_INT_SAR] = C_IRQ3; - irq_hwmask[MSP_INT_SEC] = C_IRQ5; - #endif /* CONFIG_MIPS_MT_SMP */ #endif /* CONFIG_MIPS_MT */ /* setup the cascaded interrupts */ @@ -153,8 +145,10 @@ void __init arch_init_irq(void) setup_irq(MSP_INT_PER, &per_cascade_msp); #else - /* setup the 2nd-level SLP register based interrupt controller */ - /* VSMP /SMTC support support is not enabled for SLP */ + /* + * Setup the 2nd-level SLP register based interrupt controller. + * VSMP support support is not enabled for SLP. + */ msp_slp_irq_init(); /* setup the cascaded SLP/PER interrupts */ |