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| author | James Morris <jmorris@namei.org> | 2009-05-08 17:56:47 +1000 |
|---|---|---|
| committer | James Morris <jmorris@namei.org> | 2009-05-08 17:56:47 +1000 |
| commit | d254117099d711f215e62427f55dfb8ebd5ad011 (patch) | |
| tree | 0848ff8dd74314fec14a86497f8d288c86ba7c65 /arch/m32r/include/asm/cachectl.h | |
| parent | 07ff7a0b187f3951788f64ae1f30e8109bc8e9eb (diff) | |
| parent | 8c9ed899b44c19e81859fbb0e9d659fe2f8630fc (diff) | |
Merge branch 'master' into next
Diffstat (limited to 'arch/m32r/include/asm/cachectl.h')
| -rw-r--r-- | arch/m32r/include/asm/cachectl.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/m32r/include/asm/cachectl.h b/arch/m32r/include/asm/cachectl.h new file mode 100644 index 000000000000..2aab8f6fff41 --- /dev/null +++ b/arch/m32r/include/asm/cachectl.h @@ -0,0 +1,26 @@ +/* + * cachectl.h -- defines for M32R cache control system calls + * + * Copyright (C) 2003 by Kazuhiro Inaoka + */ +#ifndef __ASM_M32R_CACHECTL +#define __ASM_M32R_CACHECTL + +/* + * Options for cacheflush system call + * + * cacheflush() is currently fluch_cache_all(). + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +/* + * Caching modes for the cachectl(2) call + * + * cachectl(2) is currently not supported and returns ENOSYS. + */ +#define CACHEABLE 0 /* make pages cacheable */ +#define UNCACHEABLE 1 /* make pages uncacheable */ + +#endif /* __ASM_M32R_CACHECTL */ |