diff options
| author | Abhimanyu Kapur <abhimany@codeaurora.org> | 2016-02-12 17:27:36 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:08:52 -0700 |
| commit | c36ce4acc9fc1e66f0edfe5ebee02b89a60d7232 (patch) | |
| tree | a39a384c59830705ecd404d221030a517dd35677 /arch/arm64 | |
| parent | 7ae4a36f579ab6deaf17036558b6b33fc76fa04b (diff) | |
drivers: GICv3: Add mb() after the read of the IAR1_EL1 and other registers
As per the GICv3 architecture spec section "Observability
of GIC Register Accsses", architecture execution of the "DSB"
gurantees that last interrupt identifier read from ICC_IAR{0,1}_EL1
is observable by the top-level Distributor and by accesses from
any processor to the top-level Distributor.
Same comment goes for the ICC_PMR_EL1 and ICC_SGI1R_EL1 too.
CRs-Fixed: 960754
Change-Id: I9c7bcdee51f71d369e2a6f04faf7a22c3c1381bc
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
[abhimany: relocate mb()'s to header files]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/include/asm/arch_gicv3.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 2731d3b25ed2..8e159f250026 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -103,6 +103,8 @@ static inline u64 gic_read_iar_common(void) u64 irqstat; asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); + /* As per the architecture specification */ + mb(); return irqstat; } @@ -131,6 +133,8 @@ static inline u64 gic_read_iar_cavium_thunderx(void) static inline void gic_write_pmr(u32 val) { asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val)); + /* As per the architecture specification */ + mb(); } static inline void gic_write_ctlr(u32 val) @@ -148,6 +152,8 @@ static inline void gic_write_grpen1(u32 val) static inline void gic_write_sgi1r(u64 val) { asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); + /* As per the architecture specification */ + mb(); } static inline u32 gic_read_sre(void) |