diff options
| author | James Morse <james.morse@arm.com> | 2016-04-27 17:47:07 +0100 |
|---|---|---|
| committer | Mohammed Khajapasha <mkhaja@codeaurora.org> | 2017-04-19 11:35:47 +0530 |
| commit | 48dcef3717f74cc0ea1aea9dd923c06961b7a2b0 (patch) | |
| tree | 5483face6a0f44ea1c0b16d17261613b8f4af8d6 /arch/arm64/kernel/head.S | |
| parent | 9a59cd54291278483ee1b52106167a25e7b65ddb (diff) | |
arm64: Change cpu_resume() to enable mmu early then access sleep_sp by va
By enabling the MMU early in cpu_resume(), the sleep_save_sp and stack can
be accessed by VA, which avoids the need to convert-addresses and clean to
PoC on the suspend path.
MMU setup is shared with the boot path, meaning the swapper_pg_dir is
restored directly: ttbr1_el1 is no longer saved/restored.
struct sleep_save_sp is removed, replacing it with a single array of
pointers.
cpu_do_{suspend,resume} could be further reduced to not restore: cpacr_el1,
mdscr_el1, tcr_el1, vbar_el1 and sctlr_el1, all of which are set by
__cpu_setup(). However these values all contain res0 bits that may be used
to enable future features.
Change-Id: I9a188fe2600914463ca30d7515db48851f12a7fe
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-commit: cabe1c81ea5be983425d117912d7883e252a3b09
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Mohammed Khajapasha <mkhaja@codeaurora.org>
Diffstat (limited to 'arch/arm64/kernel/head.S')
| -rw-r--r-- | arch/arm64/kernel/head.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 702bc2022b85..a1c2ac38771d 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -663,7 +663,7 @@ ENDPROC(__secondary_switched) * If it isn't, park the CPU */ .section ".idmap.text", "ax" -__enable_mmu: +ENTRY(__enable_mmu) mrs x22, sctlr_el1 // preserve old SCTLR_EL1 value mrs x1, ID_AA64MMFR0_EL1 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 |