diff options
| author | Lina Iyer <ilina@codeaurora.org> | 2016-02-23 13:08:31 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-04-26 14:37:59 -0700 |
| commit | abc784c00c8365e9cfb4dd3514c012d17cf7a993 (patch) | |
| tree | 1289d05614ca32e50e4c6c9865fd1cb76eff724f /Documentation | |
| parent | f9c1246a81031fd886071139f05da568ed1767d7 (diff) | |
drivers: thermal: add LMH-DCVS driver
The Limits Management Hardware (LMH-DCVS) is a hardware block for
monitoring thermal profiles and taking immediate action to control
temperature without software intervention. The h/w block can only be
configured under secure mode.
The LMH-DCVS block reads CPU temperatures of a cluster by sensing
information from the TSENS hardware and determines the course of action.
When enabled, the h/w triggers when the high threshold is hit for any
CPU in the cluster. The mitigative action is frequency and voltage
control that is provided to the OSM hardware.
The driver registers a virtual thermal zone device for each hardware
instance. The thermal zone device is used to set the thresholds for the
hardware to work on. Once the thresholds are setup and the trip type is
enabled, the hardware functions autonomously. Mitigative action is
completely controlled in the h/w.
Writing to the actual hardware is done through the SCM call.
Change-Id: I70d4bc387717491256fec1ef6bd8cd6a28ea641b
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/cpus.txt | 7 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/arm/msm/lmh-dcvs.txt | 24 |
2 files changed, 31 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 71314d5ab0d8..9a9c045dbf6a 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -240,6 +240,13 @@ nodes to be present and contain the properties described below. Value type: <phandle> Definition: Specifies the ACC[2] node associated with this CPU. + - qcom,lmh-dcvs: + Usage: optional and only defined for those SoC's that support + LMH DCVS hardware block + Value type: <phandle> + Definition: Specifies the LMH device that is associated with + with this CPU. + - cpu-idle-states Usage: Optional Value type: <prop-encoded-array> diff --git a/Documentation/devicetree/bindings/arm/msm/lmh-dcvs.txt b/Documentation/devicetree/bindings/arm/msm/lmh-dcvs.txt new file mode 100644 index 000000000000..26d6e65dfee9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/lmh-dcvs.txt @@ -0,0 +1,24 @@ +Limits Management Hardware - DCVS + +The LMH-DCVS block is a hardware IP for every CPU cluster, to handle quick +changes in thermal limits. The hardware responds to thermal variation amongst +the CPUs in the cluster by requesting limits on the clock frequency and +voltage on the OSM hardware. + +The LMH DCVS driver exports a virtual sensor that can be used to set the +thermal limits on the hardware. The thermal zone is not capable of reading out +a temperature. + +Properties: + +- compatible: + Usage: required + Value type: <string> + Definition: shall be "qcom,msm-hw-limits" + +Example: + + lmh_dcvs0: qcom,limits-dcvs@0 { + compatible = "qcom,msm-hw-limits"; + }; + |