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| author | Pavankumar Kondeti <pkondeti@codeaurora.org> | 2015-05-07 17:14:48 +0530 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:25:59 -0700 |
| commit | 6c98c21f9e7253ba25b831bd13852e295b341cfa (patch) | |
| tree | e7a2d445c52e86f542a5392f7673f7ce5d71bbf1 /Documentation | |
| parent | 5796af4921425206827a6005412f43622cbfc0db (diff) | |
arm64: topology: Allow specifying the CPU efficiency from device tree
The efficiency of a CPU can vary across SoCs depending on the cache size,
bus interconnect frequencies etc. Allow specifying this from the device
tree. This value overrides the default values hardcoded in the efficiency
table.
Change-Id: Ie9ba69e11317e6eb6462630226355747d1def646
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/cpus.txt | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3a07a87fef20..71314d5ab0d8 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -212,6 +212,20 @@ nodes to be present and contain the properties described below. property identifying a 64-bit zero-initialised memory location. + - efficiency + Usage: optional. + Value type: <u32> + Definition: + # Specifies the CPU efficiency. The CPU efficiency is + a unit less number and it is intended to show relative + performance of CPUs when normalized for clock frequency + (instructions per cycle performance). + + The efficiency of a CPU can vary across SoCs depending + on the cache size, bus interconnect frequencies etc. + This value overrides the default efficiency value + defined for the corresponding CPU architecture. + - qcom,saw Usage: required for systems that have an "enable-method" property value of "qcom,kpss-acc-v1" or |