Merge "msm: pcie: support configurable wr halt size for PCIe"

1 files changed, 3 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt
index 21b6d99424c0..a50e0c2b2c35 100644
--- a/Documentation/devicetree/bindings/pci/msm_pcie.txt
+++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt
@@ -93,6 +93,8 @@ Optional Properties:
     and assign for each endpoint.
   - qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become
     stable after power on, before de-assert the PERST to the endpoint.
+  - qcom,wr-halt-size: With base 2, this exponent determines the size of the
+    data that PCIe core will halt on for each write transaction.
   - qcom,cpl-timeout: Completion timeout value. This value specifies the time range
     which the root complex will send out a completion packet if there is no response
     from the endpoint.
@@ -270,6 +272,7 @@ Example:
 		qcom,smmu-exist;
 		qcom,smmu-sid-base = <0x1480>;
 		qcom,ep-latency = <100>;
+		qcom,wr-halt-size = <0xa>; /* 1KB */
 		qcom,cpl-timeout = <0x2>;
 
 		iommus = <&anoc0_smmu>;