diff options
| author | Andrew Pinski <apinski@cavium.com> | 2016-02-24 17:44:57 -0800 |
|---|---|---|
| committer | Sami Tolvanen <samitolvanen@google.com> | 2016-09-29 10:52:56 -0700 |
| commit | 3e64a8612dfa8738b95ad904a454b859ec9d9174 (patch) | |
| tree | 611b1f34ae50f7d0efcbe88b7e40f9838dbc8664 /Documentation/arm64 | |
| parent | d5f46e4b247971c9c10f902151dcf7df8c750b1c (diff) | |
UPSTREAM: arm64: Add workaround for Cavium erratum 27456
On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
instructions may cause the icache to become corrupted if it contains
data for a non-current ASID.
This patch implements the workaround (which invalidates the local
icache when switching the mm) by using code patching.
Signed-off-by: Andrew Pinski <apinski@cavium.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Change-Id: I60e6d17926b067a4e022d7b159e239114303a547
(cherry picked from commit 104a0c02e8b1936c049e18a6d4e4ab040fb61213)
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Diffstat (limited to 'Documentation/arm64')
| -rw-r--r-- | Documentation/arm64/silicon-errata.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 58b71ddf9b60..ba4b6acfc545 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -56,3 +56,4 @@ stable kernels. | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | |