diff options
| author | Yan He <yanhe@codeaurora.org> | 2015-04-08 16:17:10 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:16:05 -0700 |
| commit | f7fa70a57d712a37a1197a265eaeecd5110008d1 (patch) | |
| tree | 36b382cde90a3dc659b2f799ee03fa206e9a5166 | |
| parent | 4b39cc2da0c8e0637ca3a8d92312324b08b910db (diff) | |
msm: ep_pcie: correct PME configuration
Correct the PME configuration for PCIe endpoint to support D0, D3
hot and D3 cold.
Change-Id: Ib906fbafc490be75e5f178176e33882c392d074e
Signed-off-by: Yan He <yanhe@codeaurora.org>
| -rw-r--r-- | drivers/platform/msm/ep_pcie/ep_pcie_core.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 162e7c920abb..05cad05f9b33 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -510,7 +510,7 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev) /* Set the PMC Register - to support PME in D0, D3hot and D3cold */ ep_pcie_write_mask(dev->dm_core + PCIE20_CAP_ID_NXT_PTR, 0, - BIT(4)|BIT(3)|BIT(0)); + BIT(31)|BIT(30)|BIT(27)); /* Set the Endpoint L0s Acceptable Latency to 1us (max) */ ep_pcie_write_reg_field(dev->dm_core, PCIE20_DEVICE_CAPABILITIES, |