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| author | Saranya Chidura <schidura@codeaurora.org> | 2017-02-09 09:55:39 +0530 |
|---|---|---|
| committer | Saranya Chidura <schidura@codeaurora.org> | 2017-02-14 10:30:14 +0530 |
| commit | f76d422d2ca0ad06cb13499ca774450e6dd6dd76 (patch) | |
| tree | 9bbf9eac78b7048fef481b5328cd699a0640d191 | |
| parent | 3a7e752617514960c5cecdf84e12b13dc63c04c7 (diff) | |
ARM: dts: msm: enable etr as default sink on sdm660
Coresight ETR sink is enabled as the default sink to
collect traces.
Change-Id: I78cec888284307dbc7e696e7b33b45707bf9e1ca
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/sdm660-coresight.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi b/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi index 431da5036a4b..dce86a7ceec3 100644 --- a/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi @@ -25,6 +25,7 @@ arm,buffer-size = <0x400000>; arm,sg-enable; + arm,default-sink; coresight-ctis = <&cti0 &cti8>; |