qcacmn: Fix kernel module check patch warnings in HIF PCI files

Fix kernel module check patch warnings in HIF PCI files

Change-Id: Id3bedc47c3b39666240a9aa0717d0f931f77ee63
CRs-fixed: 2033001

1 files changed, 50 insertions, 41 deletions

diff --git a/hif/src/pcie/if_pci.c b/hif/src/pcie/if_pci.c
index df657a185a9c..b767cc291b34 100644
--- a/hif/src/pcie/if_pci.c
+++ b/hif/src/pcie/if_pci.c
@@ -86,7 +86,6 @@ struct ce_irq_reg_table {
 #ifndef QCA_WIFI_3_0_ADRASTEA
 static inline void hif_pci_route_adrastea_interrupt(struct hif_pci_softc *sc)
 {
-	return;
 }
 #else
 void hif_pci_route_adrastea_interrupt(struct hif_pci_softc *sc)
@@ -146,9 +145,8 @@ static void pci_dispatch_interrupt(struct hif_softc *scn)
 		}
 		Q_TARGET_ACCESS_END(scn);
 		return;
-	} else {
-		Q_TARGET_ACCESS_END(scn);
 	}
+	Q_TARGET_ACCESS_END(scn);
 
 	scn->ce_irq_summary = intr_summary;
 	for (id = 0; intr_summary && (id < scn->ce_count); id++) {
@@ -164,6 +162,7 @@ irqreturn_t hif_pci_interrupt_handler(int irq, void *arg)
 	struct hif_pci_softc *sc = (struct hif_pci_softc *)arg;
 	struct hif_softc *scn = HIF_GET_SOFTC(sc);
 	struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(arg);
+
 	volatile int tmp;
 	uint16_t val;
 	uint32_t bar0;
@@ -189,7 +188,8 @@ irqreturn_t hif_pci_interrupt_handler(int irq, void *arg)
 		/* Clear Legacy PCI line interrupts
 		 * IMPORTANT: INTR_CLR regiser has to be set
 		 * after INTR_ENABLE is set to 0,
-		 * otherwise interrupt can not be really cleared */
+		 * otherwise interrupt can not be really cleared
+		 */
 		hif_write32_mb(sc->mem +
 			      (SOC_CORE_BASE_ADDRESS |
 			       PCIE_INTR_ENABLE_ADDRESS), 0);
@@ -201,10 +201,11 @@ irqreturn_t hif_pci_interrupt_handler(int irq, void *arg)
 			      HOST_GROUP0_MASK);
 
 		if (ADRASTEA_BU)
-			hif_write32_mb(sc->mem + 0x2f100c , (host_cause >> 1));
+			hif_write32_mb(sc->mem + 0x2f100c, (host_cause >> 1));
 
 		/* IMPORTANT: this extra read transaction is required to
-		 * flush the posted write buffer */
+		 * flush the posted write buffer
+		 */
 		if (!ADRASTEA_BU) {
 		tmp =
 			hif_read32_mb(sc->mem +
@@ -335,7 +336,6 @@ void hif_pci_cancel_deferred_target_sleep(struct hif_softc *scn)
 #else
 inline void hif_pci_cancel_deferred_target_sleep(struct hif_softc *scn)
 {
-	return;
 }
 #endif
 
@@ -391,15 +391,14 @@ static void hif_pci_device_reset(struct hif_pci_softc *sc)
 		return;
 
 	/* NB: Don't check resetok here.  This form of reset
-	 * is integral to correct operation. */
+	 * is integral to correct operation.
+	 */
 
-	if (!SOC_GLOBAL_RESET_ADDRESS) {
+	if (!SOC_GLOBAL_RESET_ADDRESS)
 		return;
-	}
 
-	if (!mem) {
+	if (!mem)
 		return;
-	}
 
 	HIF_ERROR("%s: Reset Device", __func__);
 
@@ -461,11 +460,11 @@ static void hif_pci_device_warm_reset(struct hif_pci_softc *sc)
 	struct hif_softc *scn = HIF_GET_SOFTC(sc);
 
 	/* NB: Don't check resetok here.  This form of reset is
-	 * integral to correct operation. */
+	 * integral to correct operation.
+	 */
 
-	if (!mem) {
+	if (!mem)
 		return;
-	}
 
 	HIF_INFO_MED("%s: Target Warm Reset", __func__);
 
@@ -734,7 +733,8 @@ static void __hif_pci_dump_registers(struct hif_softc *scn)
 					      val);
 
 				/* read (@gpio_athr_wlan_reg)
-				 * WLAN_DEBUG_OUT_DATA */
+				 * WLAN_DEBUG_OUT_DATA
+				 */
 				val = hif_read32_mb(mem + GPIO_BASE_ADDRESS +
 						   WLAN_DEBUG_OUT_OFFSET);
 				val = WLAN_DEBUG_OUT_DATA_GET(val);
@@ -855,7 +855,6 @@ static void reschedule_tasklet_work_handler(void *arg)
 	}
 
 	tasklet_schedule(&sc->intr_tq);
-	return;
 }
 
 /**
@@ -1075,7 +1074,7 @@ static const struct file_operations hif_pci_runtime_pm_fops = {
 static void hif_runtime_pm_debugfs_create(struct hif_pci_softc *sc)
 {
 	sc->pm_dentry = debugfs_create_file("cnss_runtime_pm",
-					S_IRUSR, NULL, sc,
+					0400, NULL, sc,
 					&hif_pci_runtime_pm_fops);
 }
 
@@ -1242,7 +1241,7 @@ static void hif_pm_runtime_sanitize_on_ssr_exit(struct hif_pci_softc *sc)
 
 	spin_lock_bh(&sc->runtime_lock);
 	list_for_each_entry_safe(ctx, tmp, &sc->prevent_suspend_list, list) {
-		 __hif_pm_runtime_allow_suspend(sc, ctx);
+		__hif_pm_runtime_allow_suspend(sc, ctx);
 	}
 	spin_unlock_bh(&sc->runtime_lock);
 }
@@ -1539,7 +1538,8 @@ static void hif_set_hia_extnd(struct hif_softc *scn)
 			target_type == TARGET_TYPE_QCA9984 ||
 			target_type == TARGET_TYPE_QCA9888) {
 		/* CHIP revision is 8-11 bits of the CHIP_ID register 0xec
-		in RTC space */
+		 * in RTC space
+		 */
 		tgt_info->target_revision
 			= CHIP_ID_REVISION_GET(hif_read32_mb(scn->mem
 					+ CHIP_ID_ADDRESS));
@@ -1578,7 +1578,8 @@ static void hif_set_hia_extnd(struct hif_softc *scn)
 		 * Assume 1.0 clock can't be tuned, reset to defaults
 		 */
 
-		qdf_print(KERN_INFO"%s: setting the target pll frac %x intval %x\n",
+		qdf_print(KERN_INFO
+			  "%s: setting the target pll frac %x intval %x\n",
 			  __func__, frac, intval);
 
 		/* do not touch frac, and int val, let them be default -1,
@@ -1602,7 +1603,8 @@ static void hif_set_hia_extnd(struct hif_softc *scn)
 			hif_diag_write_access(hif_hdl,
 					flag2_value + 4, intval);
 		} else {
-			qdf_print(KERN_INFO"%s: no frac provided, skipping pre-configuring PLL\n",
+			qdf_print(KERN_INFO
+				  "%s: no frac provided, skipping pre-configuring PLL\n",
 				  __func__);
 		}
 
@@ -1619,7 +1621,7 @@ static void hif_set_hia_extnd(struct hif_softc *scn)
 					hi_desired_cpu_speed_hz));
 			hif_diag_read_access(hif_hdl, flag2_targ_addr,
 							&flag2_value);
-			qdf_print("\n ====> hi_desired_cpu_speed_hz Address %x\n",
+			qdf_print("\n ==> hi_desired_cpu_speed_hz Address %x\n",
 				  flag2_value);
 			hif_diag_write_access(hif_hdl, flag2_value,
 				ar900b_20_targ_clk/*300000000u*/);
@@ -2044,6 +2046,7 @@ timer_free:
 void hif_pci_close(struct hif_softc *hif_sc)
 {
 	struct hif_pci_softc *hif_pci_sc = HIF_GET_PCI_SOFTC(hif_sc);
+
 	hif_pm_runtime_close(hif_pci_sc);
 	hif_ce_close(hif_sc);
 }
@@ -2092,7 +2095,8 @@ static int hif_enable_pci(struct hif_pci_softc *sc,
 	}
 #ifdef CONFIG_ARM_LPAE
 	/* if CONFIG_ARM_LPAE is enabled, we have to set 64 bits mask
-	 * for 32 bits device also. */
+	 * for 32 bits device also.
+	 */
 	ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
 	if (ret) {
 		HIF_ERROR("%s: Cannot enable 64-bit pci DMA", __func__);
@@ -2202,17 +2206,18 @@ static int hif_pci_probe_tgt_wakeup(struct hif_pci_softc *sc)
 		while (wait_limit-- &&
 			   !(hif_read32_mb(sc->mem +
 					  PCIE_LOCAL_BASE_ADDRESS +
-					  PCIE_SOC_RDY_STATUS_ADDRESS) \
+					  PCIE_SOC_RDY_STATUS_ADDRESS)
 					  & PCIE_SOC_RDY_STATUS_BAR_MASK)) {
 			qdf_mdelay(10);
 		}
 		if (wait_limit < 0) {
-			/* AR6320v1 doesn't support checking of BAR0 configuration,
-				 takes one sec to wait BAR0 ready */
+			/* AR6320v1 doesn't support checking of BAR0
+			 * configuration, takes one sec to wait BAR0 ready
+			 */
 			HIF_INFO_MED("%s: AR6320v1 waits two sec for BAR0",
 				    __func__);
 		}
-    }
+	}
 #endif
 
 #ifndef QCA_WIFI_3_0
@@ -2379,7 +2384,7 @@ static int hif_configure_msi(struct hif_pci_softc *sc)
 	return ret;
 
 err_intr:
-if (sc->num_msi_intrs >= 1)
+	if (sc->num_msi_intrs >= 1)
 		pci_disable_msi(sc->pdev);
 	return ret;
 }
@@ -2402,7 +2407,8 @@ static int hif_pci_configure_legacy_irq(struct hif_pci_softc *sc)
 		goto end;
 	}
 	/* Use sc->irq instead of sc->pdev-irq
-	platform_device pdev doesn't have an irq field */
+	 * platform_device pdev doesn't have an irq field
+	 */
 	sc->irq = sc->pdev->irq;
 	/* Use Legacy PCI Interrupts */
 	hif_write32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS |
@@ -2446,14 +2452,14 @@ void hif_pci_nointrs(struct hif_softc *scn)
 		return;
 	if (sc->num_msi_intrs > 0) {
 		/* MSI interrupt(s) */
-		for (i = 0; i < sc->num_msi_intrs; i++) {
+		for (i = 0; i < sc->num_msi_intrs; i++)
 			free_irq(sc->irq + i, sc);
-		}
 		sc->num_msi_intrs = 0;
 	} else {
 		/* Legacy PCI line interrupt
-		Use sc->irq instead of sc->pdev-irq
-		platform_device pdev doesn't have an irq field */
+		 * Use sc->irq instead of sc->pdev-irq
+		 * platform_device pdev doesn't have an irq field
+		 */
 		free_irq(sc->irq, sc);
 	}
 	ce_unregister_irq(hif_state, 0xfff);
@@ -2496,7 +2502,8 @@ void hif_pci_disable_bus(struct hif_softc *scn)
 	 * Need to enable for AR9888_REV1 once CPU warm reset sequence is
 	 * verified for AR9888_REV1
 	 */
-	if ((tgt_info->target_version == AR9888_REV2_VERSION) || (tgt_info->target_version == AR9887_REV1_VERSION))
+	if ((tgt_info->target_version == AR9888_REV2_VERSION) ||
+	    (tgt_info->target_version == AR9887_REV1_VERSION))
 		hif_pci_device_warm_reset(sc);
 	else
 		hif_pci_device_reset(sc);
@@ -2829,6 +2836,7 @@ static void hif_runtime_pm_set_state_suspended(struct hif_softc *scn)
 static void hif_log_runtime_suspend_success(struct hif_softc *hif_ctx)
 {
 	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx);
+
 	if (sc == NULL)
 		return;
 
@@ -2845,6 +2853,7 @@ static void hif_log_runtime_suspend_success(struct hif_softc *hif_ctx)
 static void hif_log_runtime_suspend_failure(void *hif_ctx)
 {
 	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx);
+
 	if (sc == NULL)
 		return;
 
@@ -2860,6 +2869,7 @@ static void hif_log_runtime_suspend_failure(void *hif_ctx)
 static void hif_log_runtime_resume_success(void *hif_ctx)
 {
 	struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(hif_ctx);
+
 	if (sc == NULL)
 		return;
 
@@ -3243,12 +3253,9 @@ int hif_pci_target_sleep_state_adjust(struct hif_softc *scn,
 				if (hif_targ_is_awake(scn, pci_addr)) {
 					hif_state->verified_awake = true;
 					break;
-				} else
-				if (!hif_pci_targ_is_present
-					    (scn, pci_addr)) {
-					break;
 				}
-
+				if (!hif_pci_targ_is_present(scn, pci_addr))
+					break;
 				if (tot_delay > PCIE_SLEEP_ADJUST_TIMEOUT)
 					return hif_log_soc_wakeup_timeout(sc);
 
@@ -3448,6 +3455,7 @@ static void hif_target_sync(struct hif_softc *scn)
 	if (HAS_FW_INDICATOR) {
 		int wait_limit = 500;
 		int fw_ind = 0;
+
 		HIF_TRACE("%s: Loop checking FW signal", __func__);
 		while (1) {
 			fw_ind = hif_read32_mb(scn->mem +
@@ -3760,7 +3768,8 @@ int hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx)
 
 
 /**
- * __hif_pm_runtime_prevent_suspend() - prevent runtime suspend for a protocol reason
+ * __hif_pm_runtime_prevent_suspend() - prevent runtime suspend for a protocol
+ *                                      reason
  * @hif_sc: pci context
  * @lock: runtime_pm lock being acquired
  *