diff options
| author | Veerabhadrarao Badiganti <vbadigan@codeaurora.org> | 2017-09-12 14:41:39 +0530 |
|---|---|---|
| committer | Veerabhadrarao Badiganti <vbadigan@codeaurora.org> | 2017-09-12 16:24:25 +0530 |
| commit | f4e489e4c055e2ac3ddb5747fbf0f38d2e4684f8 (patch) | |
| tree | d7a03d32a5be02a160da842fbbe858b8fd907448 | |
| parent | 739a7c1e43627a90e5a89644bb31b01a877cd312 (diff) | |
mmc: host: sdhci-msm: Enable SDHC FIFO explicitly
Enable SDHC FIFO explicitly by disabling the alternative FIFO.
The boot-loaders might use alternative FIFO instead of HC FIFO.
And the vendor specific register which has this setting won't get
reset with controller reset. So the FIFO setting done by the
bootloader would remain as it is unless its explicitly cleared.
Without clearing this setting, mmc driver can't make use of regular
FIFO mode.
Change-Id: I8c7ff9b20c33518fb9013cce2f9284117fc2ce3c
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
| -rw-r--r-- | drivers/mmc/host/sdhci-msm.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index ab4837128cb2..6d70e8d6bfb3 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -142,6 +142,7 @@ #define CORE_START_CDC_TRAFFIC (1 << 6) #define CORE_PWRSAVE_DLL (1 << 3) +#define CORE_FIFO_ALT_EN (1 << 10) #define CORE_CMDEN_HS400_INPUT_MASK_CNT (1 << 13) #define CORE_DDR_CAL_EN (1 << 0) @@ -4484,6 +4485,14 @@ static int sdhci_msm_probe(struct platform_device *pdev) writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC); + /* + * Ensure SDHCI FIFO is enabled by disabling alternative FIFO + */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3) & + ~CORE_FIFO_ALT_EN), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3); + if (!msm_host->mci_removed) { /* Set HC_MODE_EN bit in HC_MODE register */ writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); |