diff options
| author | Stepan Moskovchenko <stepanm@codeaurora.org> | 2014-06-05 16:06:59 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:03:14 -0700 |
| commit | f41560721c438d77b2a86c91a6ea363c191558a0 (patch) | |
| tree | 36475903797852a8f5360de3c9831102b253f849 | |
| parent | 75defbf36753b7737d0007bf261335300587439f (diff) | |
arm64: Add options to disable I/D caches
Add the ability to individually disable the Instruction and
Data caches on ARM64 CPUs, by means of the SCTLR[I] and
SCTLR[C] bits. This may be useful for performance
profiling, as well as for troubleshooting potential cache
problems.
Change-Id: Ibd7fc796ddf6984c7f05dcd844432164e28bb021
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
[abhimany: resolve trivial merge conflicts]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
| -rw-r--r-- | arch/arm64/Kconfig | 19 | ||||
| -rw-r--r-- | arch/arm64/mm/proc.S | 13 |
2 files changed, 31 insertions, 1 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 8912034a5d0e..ae7d259140ce 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -456,6 +456,25 @@ config ARM64_16K_PAGES requires applications compiled with 16K (or a multiple of 16K) aligned segments. +config ARM64_DCACHE_DISABLE + bool "Disable CPU Data Caches" + help + Disable CPU data cache usage by setting the SCTLR[C] bit during + kernel initialization. This will result in a considerable + performance impact, but may be useful in certain situations. + + If you are not sure what to do, select 'N' here. + +config ARM64_ICACHE_DISABLE + bool "Disable CPU Instruction Caches" + help + Disable CPU instruction cache usage by setting the SCTLR[I] + bit during kernel initialization. This will result in a + considerable performance impact, but may be useful in certain + situations. + + If you are not sure what to do, select 'N' here. + config ARM64_64K_PAGES bool "64KB" help diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index f62f0356a3bf..f0dd47a5a532 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -273,5 +273,16 @@ ENDPROC(__cpu_setup) */ .type crval, #object crval: +#ifdef CONFIG_ARM64_ICACHE_DISABLE +#define CR_IBIT 0 +#else +#define CR_IBIT 0x1000 +#endif + +#ifdef CONFIG_ARM64_DCACHE_DISABLE +#define CR_CBIT 0 +#else +#define CR_CBIT 0x4 +#endif .word 0xfcffffff // clear - .word 0x34d5d91d // set + .word 0x34d5d91d | CR_IBIT | CR_CBIT // set |