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authorYan He <yanhe@codeaurora.org>2015-05-29 14:31:29 -0700
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-22 11:16:08 -0700
commitf31be11ecb7d33f4dccfbcc358ca059b214b3c5c (patch)
tree1b78c86a083ba188e3b4c54c14fc642f1725cfb5
parenta0ad90f548fa9e562053d05b6875fe425eb1869d (diff)
msm: ep_pcie: disable debouncers
Disable debouncers for PCIe endpoint mode. Change-Id: I504418193920861296d995bd898f01307e6dc518 Signed-off-by: Yan He <yanhe@codeaurora.org>
-rw-r--r--drivers/platform/msm/ep_pcie/ep_pcie_com.h1
-rw-r--r--drivers/platform/msm/ep_pcie/ep_pcie_core.c3
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h
index 6c4d69a2d459..131e0eaa31e1 100644
--- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h
+++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h
@@ -24,6 +24,7 @@
#include <linux/msm_ep_pcie.h>
#define PCIE20_PARF_SYS_CTRL 0x00
+#define PCIE20_PARF_DB_CTRL 0x10
#define PCIE20_PARF_PM_CTRL 0x20
#define PCIE20_PARF_PM_STTS 0x24
#define PCIE20_PARF_PHY_CTRL 0x40
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c
index 2a646c166d7f..0b8517e5b8b7 100644
--- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c
+++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c
@@ -489,6 +489,9 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev)
/* Disable the DBI Wakeup */
ep_pcie_write_mask(dev->parf + PCIE20_PARF_SYS_CTRL, BIT(11), 0);
+ /* Disable the debouncers */
+ ep_pcie_write_reg(dev->parf, PCIE20_PARF_DB_CTRL, 0x73);
+
/* Disable core clock CGC */
ep_pcie_write_mask(dev->parf + PCIE20_PARF_SYS_CTRL, 0, BIT(6));