clk: msm: mdss: fix pclk_src_mux clock ops for DSI PLL on msmcobalt

The DSI pixel clock path in the DSI PLL has a mux clock (pclk_src_mux)
which allows the pixel clock to be either sourced out of the VCO clock
or the bitclock.  In the current code, the ops for this mux clock is
overloaded incorrectly which results in the pixel clock being always
sourced out of the bit clock. Fix this by using the default mux clock
ops for this clock.

Change-Id: I39c23b52d17994e28bd3b0d93e8e3dabdb687940
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c b/drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c
index 64b7f4d6dae5..61351084bc48 100644
--- a/drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c
+++ b/drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c
@@ -1025,7 +1025,7 @@ static struct mux_clk dsi0pll_pclk_src_mux = {
 	.c = {
 		.parent = &dsi0pll_post_bit_div.c,
 		.dbg_name = "dsi0pll_pclk_src_mux",
-		.ops = &clk_ops_gen_mux_dsi,
+		.ops = &clk_ops_gen_mux,
 		.flags = CLKFLAG_NO_RATE_CACHE,
 		CLK_INIT(dsi0pll_pclk_src_mux.c),
 	}
@@ -1162,7 +1162,7 @@ static struct mux_clk dsi1pll_pclk_src_mux = {
 	.c = {
 		.parent = &dsi1pll_post_bit_div.c,
 		.dbg_name = "dsi1pll_pclk_src_mux",
-		.ops = &clk_ops_gen_mux_dsi,
+		.ops = &clk_ops_gen_mux,
 		.flags = CLKFLAG_NO_RATE_CACHE,
 		CLK_INIT(dsi1pll_pclk_src_mux.c),
 	}