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authorShivaraj Shetty <shivaraj@codeaurora.org>2014-10-21 23:46:37 +0530
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-23 20:35:12 -0700
commitf07d12346cfe8060483fa76aafdf2d7f3b104f43 (patch)
tree1ad9ea3246b6b4d768200e78c199e899c7f027f2
parentc2539b44b3354c600468bf9589c372142ed20f9b (diff)
msm: mdss: Move double bufferring mode support for dsi to dtsi
Move double bufferring mode support property for dsi controller to dtsi as it is not supported on 8909. Change-Id: I2d99c34af7d4b9eef8f4503bad6fcd1480b2bde6 Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
-rw-r--r--Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt2
-rw-r--r--drivers/video/fbdev/msm/mdss_dsi.c3
-rw-r--r--drivers/video/fbdev/msm/mdss_dsi.h1
-rw-r--r--drivers/video/fbdev/msm/mdss_dsi_host.c9
4 files changed, 9 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt
index 7ad0f2769ba8..d2c6f085c1de 100644
--- a/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt
@@ -75,6 +75,7 @@ Optional properties:
- qcom,mmss-ulp-clamp-ctrl-offset: Specifies the offset for dsi ulps clamp control register.
- qcom,mmss-phyreset-ctrl-offset: Specifies the offset for dsi phy reset control register.
- qcom,dsi-irq-line: Boolean specifies if DSI has a different irq line than mdp.
+- qcom,timing-db-mode: Boolean specifies dsi timing mode registers are supported or not.
Example:
mdss_dsi0: qcom,mdss_dsi@fd922800 {
@@ -113,6 +114,7 @@ Example:
qcom,platform-mode-gpio = <&msmgpio 7 0>;
qcom,dsi-panel-bias-vreg;
qcom,dsi-irq-line;
+ qcom,timing-db-mode;
qcom,core-supply-entries {
#address-cells = <1>;
diff --git a/drivers/video/fbdev/msm/mdss_dsi.c b/drivers/video/fbdev/msm/mdss_dsi.c
index 9c041b074072..d903e462d318 100644
--- a/drivers/video/fbdev/msm/mdss_dsi.c
+++ b/drivers/video/fbdev/msm/mdss_dsi.c
@@ -1803,6 +1803,9 @@ int dsi_panel_device_register(struct device_node *pan_node,
ctrl_pdata->mode_gpio = -EINVAL;
}
+ ctrl_pdata->timing_db_mode = of_property_read_bool(
+ ctrl_pdev->dev.of_node, "qcom,timing-db-mode");
+
if (mdss_dsi_clk_init(ctrl_pdev, ctrl_pdata)) {
pr_err("%s: unable to initialize Dsi ctrl clks\n", __func__);
return -EPERM;
diff --git a/drivers/video/fbdev/msm/mdss_dsi.h b/drivers/video/fbdev/msm/mdss_dsi.h
index cac9371dff0b..a420bdab8a9c 100644
--- a/drivers/video/fbdev/msm/mdss_dsi.h
+++ b/drivers/video/fbdev/msm/mdss_dsi.h
@@ -374,6 +374,7 @@ struct mdss_dsi_ctrl_pdata {
bool ulps;
bool core_power;
bool mmss_clamp;
+ bool timing_db_mode;
struct dsi_buf tx_buf;
struct dsi_buf rx_buf;
diff --git a/drivers/video/fbdev/msm/mdss_dsi_host.c b/drivers/video/fbdev/msm/mdss_dsi_host.c
index d411cd776f88..ba210d2594b4 100644
--- a/drivers/video/fbdev/msm/mdss_dsi_host.c
+++ b/drivers/video/fbdev/msm/mdss_dsi_host.c
@@ -925,7 +925,7 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data, dst_bpp;
u32 dummy_xres = 0, dummy_yres = 0;
- u32 hsync_period, vsync_period, ctrl_rev;
+ u32 hsync_period, vsync_period;
ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
panel_data);
@@ -958,9 +958,7 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
mipi = &pdata->panel_info.mipi;
if (pdata->panel_info.type == MIPI_VIDEO_PANEL) {
- ctrl_rev = MIPI_INP(ctrl_pdata->ctrl_base);
- /* Enable DSI TIMING register double buffering for 8916/8939 */
- if (ctrl_rev == MDSS_DSI_HW_REV_103_1)
+ if (ctrl_pdata->timing_db_mode)
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e8, 0x1);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x24,
((hspw + hbp + width + dummy_xres) << 16 |
@@ -975,8 +973,7 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x30, (hspw << 16));
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x34, 0);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x38, (vspw << 16));
- /* Flush DSI TIMING registers for 8916/8939 */
- if (ctrl_rev == MDSS_DSI_HW_REV_103_1)
+ if (ctrl_pdata->timing_db_mode)
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e4, 0x1);
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)